mirror of https://github.com/acidanthera/audk.git
DynamicTablesPkg: Move Continuous perf control info to Arch Common
Move the Continuous perfformance control info object from Arm Namespace to the Arch Common namespace. Correspondingly also update the following modules to reflect the changes introduced by the move: - SSDT CPU topology generator - ConfigurationManagerObjectParser - Dynamic Plat Repo TokenFixer map. Cc: Pierre Gondois <Pierre.Gondois@arm.com> Cc: Yeo Reum Yun <YeoReum.Yun@arm.com> Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com> Cc: Jeshua Smith <jeshuas@nvidia.com> Cc: Jeff Brasen <jbrasen@nvidia.com> Cc: Girish Mahadevan <gmahadevan@nvidia.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
This commit is contained in:
parent
afa7f8a6b1
commit
ff249c62e3
|
@ -38,6 +38,7 @@ typedef enum ArchCommonObjectID {
|
|||
EArchCommonObjLpiInfo, ///< 15 - Lpi Info
|
||||
EArchCommonObjProcHierarchyInfo, ///< 16 - Processor Hierarchy Info
|
||||
EArchCommonObjCacheInfo, ///< 17 - Cache Info
|
||||
EArchCommonObjCpcInfo, ///< 18 - Continuous Performance Control Info
|
||||
EArchCommonObjMax
|
||||
} EARCH_COMMON_OBJECT_ID;
|
||||
|
||||
|
@ -432,6 +433,24 @@ typedef struct CmArchCommonCacheInfo {
|
|||
UINT32 CacheId;
|
||||
} CM_ARCH_COMMON_CACHE_INFO;
|
||||
|
||||
/** A structure that describes the Cpc information.
|
||||
|
||||
Continuous Performance Control is described in DSDT/SSDT and associated
|
||||
to cpus/clusters in the cpu topology.
|
||||
|
||||
Unsupported Optional registers should be encoded with NULL resource
|
||||
Register {(SystemMemory, 0, 0, 0, 0)}
|
||||
|
||||
For values that support Integer or Buffer, integer will be used
|
||||
if buffer is NULL resource.
|
||||
If resource is not NULL then Integer must be 0
|
||||
|
||||
Cf. ACPI 6.4, s8.4.7.1 _CPC (Continuous Performance Control)
|
||||
|
||||
ID: EArchCommonObjCpcInfo
|
||||
*/
|
||||
typedef AML_CPC_INFO CM_ARCH_COMMON_CPC_INFO;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif // ARCH_COMMON_NAMESPACE_OBJECTS_H_
|
||||
|
|
|
@ -51,15 +51,14 @@ typedef enum ArmObjectID {
|
|||
EArmObjCmn600Info, ///< 20 - CMN-600 Info
|
||||
EArmObjRmr, ///< 21 - Reserved Memory Range Node
|
||||
EArmObjMemoryRangeDescriptor, ///< 22 - Memory Range Descriptor
|
||||
EArmObjCpcInfo, ///< 23 - Continuous Performance Control Info
|
||||
EArmObjPccSubspaceType0Info, ///< 24 - Pcc Subspace Type 0 Info
|
||||
EArmObjPccSubspaceType1Info, ///< 25 - Pcc Subspace Type 2 Info
|
||||
EArmObjPccSubspaceType2Info, ///< 26 - Pcc Subspace Type 2 Info
|
||||
EArmObjPccSubspaceType3Info, ///< 27 - Pcc Subspace Type 3 Info
|
||||
EArmObjPccSubspaceType4Info, ///< 28 - Pcc Subspace Type 4 Info
|
||||
EArmObjPccSubspaceType5Info, ///< 29 - Pcc Subspace Type 5 Info
|
||||
EArmObjEtInfo, ///< 30 - Embedded Trace Extension/Module Info
|
||||
EArmObjPsdInfo, ///< 31 - P-State Dependency (PSD) Info
|
||||
EArmObjPccSubspaceType0Info, ///< 23 - Pcc Subspace Type 0 Info
|
||||
EArmObjPccSubspaceType1Info, ///< 24 - Pcc Subspace Type 2 Info
|
||||
EArmObjPccSubspaceType2Info, ///< 25 - Pcc Subspace Type 2 Info
|
||||
EArmObjPccSubspaceType3Info, ///< 26 - Pcc Subspace Type 3 Info
|
||||
EArmObjPccSubspaceType4Info, ///< 27 - Pcc Subspace Type 4 Info
|
||||
EArmObjPccSubspaceType5Info, ///< 28 - Pcc Subspace Type 5 Info
|
||||
EArmObjEtInfo, ///< 29 - Embedded Trace Extension/Module Info
|
||||
EArmObjPsdInfo, ///< 30 - P-State Dependency (PSD) Info
|
||||
EArmObjMax
|
||||
} EARM_OBJECT_ID;
|
||||
|
||||
|
@ -177,7 +176,7 @@ typedef struct CmArmGicCInfo {
|
|||
UINT32 AffinityFlags;
|
||||
|
||||
/** Optional field: Reference Token for the Cpc info of this processor.
|
||||
i.e. a token referencing a CM_ARM_CPC_INFO object.
|
||||
i.e. a token referencing a CM_ARCH_COMMON_CPC_INFO object.
|
||||
*/
|
||||
CM_OBJECT_TOKEN CpcToken;
|
||||
|
||||
|
@ -715,24 +714,6 @@ typedef struct CmArmRmrDescriptor {
|
|||
UINT64 Length;
|
||||
} CM_ARM_MEMORY_RANGE_DESCRIPTOR;
|
||||
|
||||
/** A structure that describes the Cpc information.
|
||||
|
||||
Continuous Performance Control is described in DSDT/SSDT and associated
|
||||
to cpus/clusters in the cpu topology.
|
||||
|
||||
Unsupported Optional registers should be encoded with NULL resource
|
||||
Register {(SystemMemory, 0, 0, 0, 0)}
|
||||
|
||||
For values that support Integer or Buffer, integer will be used
|
||||
if buffer is NULL resource.
|
||||
If resource is not NULL then Integer must be 0
|
||||
|
||||
Cf. ACPI 6.4, s8.4.7.1 _CPC (Continuous Performance Control)
|
||||
|
||||
ID: EArmObjCpcInfo
|
||||
*/
|
||||
typedef AML_CPC_INFO CM_ARM_CPC_INFO;
|
||||
|
||||
/** A structure that describes a
|
||||
PCC Mailbox Register.
|
||||
*/
|
||||
|
|
|
@ -89,9 +89,9 @@ GET_OBJECT_LIST (
|
|||
information from the Configuration Manager.
|
||||
*/
|
||||
GET_OBJECT_LIST (
|
||||
EObjNameSpaceArm,
|
||||
EArmObjCpcInfo,
|
||||
CM_ARM_CPC_INFO
|
||||
EObjNameSpaceArchCommon,
|
||||
EArchCommonObjCpcInfo,
|
||||
CM_ARCH_COMMON_CPC_INFO
|
||||
);
|
||||
|
||||
/**
|
||||
|
@ -400,10 +400,10 @@ CreateAmlCpcNode (
|
|||
IN AML_OBJECT_NODE_HANDLE *Node
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
CM_ARM_CPC_INFO *CpcInfo;
|
||||
EFI_STATUS Status;
|
||||
CM_ARCH_COMMON_CPC_INFO *CpcInfo;
|
||||
|
||||
Status = GetEArmObjCpcInfo (
|
||||
Status = GetEArchCommonObjCpcInfo (
|
||||
CfgMgrProtocol,
|
||||
GicCInfo->CpcToken,
|
||||
&CpcInfo,
|
||||
|
|
|
@ -166,15 +166,14 @@ CM_OBJECT_TOKEN_FIXER TokenFixer[EArmObjMax] = {
|
|||
NULL, ///< 20 - CMN-600 Info
|
||||
NULL, ///< 21 - Reserved Memory Range Node
|
||||
NULL, ///< 22 - Memory Range Descriptor
|
||||
NULL, ///< 23 - Continuous Performance Control Info
|
||||
NULL, ///< 24 - Pcc Subspace Type 0 Info
|
||||
NULL, ///< 23 - Pcc Subspace Type 0 Info
|
||||
NULL, ///< 24 - Pcc Subspace Type 2 Info
|
||||
NULL, ///< 25 - Pcc Subspace Type 2 Info
|
||||
NULL, ///< 26 - Pcc Subspace Type 2 Info
|
||||
NULL, ///< 27 - Pcc Subspace Type 3 Info
|
||||
NULL, ///< 28 - Pcc Subspace Type 4 Info
|
||||
NULL, ///< 29 - Pcc Subspace Type 5 Info
|
||||
NULL, ///< 30 - Embedded Trace Extension/Module Info
|
||||
NULL ///< 31 - P-State Dependency (PSD) Info
|
||||
NULL, ///< 26 - Pcc Subspace Type 3 Info
|
||||
NULL, ///< 27 - Pcc Subspace Type 4 Info
|
||||
NULL, ///< 28 - Pcc Subspace Type 5 Info
|
||||
NULL, ///< 29 - Embedded Trace Extension/Module Info
|
||||
NULL ///< 30 - P-State Dependency (PSD) Info
|
||||
};
|
||||
|
||||
/** CmObj token fixer.
|
||||
|
|
|
@ -479,9 +479,9 @@ STATIC CONST CM_OBJ_PARSER CmArmMemoryRangeDescriptorInfoParser[] = {
|
|||
{ "Length", 8, "0x%llx", NULL },
|
||||
};
|
||||
|
||||
/** A parser for EArmObjCpcInfo.
|
||||
/** A parser for EArchCommonObjCpcInfo.
|
||||
*/
|
||||
STATIC CONST CM_OBJ_PARSER CmArmCpcInfoParser[] = {
|
||||
STATIC CONST CM_OBJ_PARSER CmArchCommonCpcInfoParser[] = {
|
||||
{ "Revision", 4, "0x%lx", NULL },
|
||||
{ "HighestPerformanceBuffer", sizeof (EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE),
|
||||
NULL, NULL, AcpiGenericAddressParser,
|
||||
|
@ -688,6 +688,7 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArchCommonNamespaceObjectParser[] = {
|
|||
CM_PARSER_ADD_OBJECT (EArchCommonObjLpiInfo, CmArchCommonLpiInfoParser),
|
||||
CM_PARSER_ADD_OBJECT (EArchCommonObjProcHierarchyInfo, CmArchCommonProcHierarchyInfoParser),
|
||||
CM_PARSER_ADD_OBJECT (EArchCommonObjCacheInfo, CmArchCommonCacheInfoParser),
|
||||
CM_PARSER_ADD_OBJECT (EArchCommonObjCpcInfo, CmArchCommonCpcInfoParser),
|
||||
CM_PARSER_ADD_OBJECT_RESERVED (EArchCommonObjMax)
|
||||
};
|
||||
|
||||
|
@ -717,7 +718,6 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArmNamespaceObjectParser[] = {
|
|||
CM_PARSER_ADD_OBJECT (EArmObjCmn600Info, CmArmCmn600InfoParser),
|
||||
CM_PARSER_ADD_OBJECT (EArmObjRmr, CmArmRmrInfoParser),
|
||||
CM_PARSER_ADD_OBJECT (EArmObjMemoryRangeDescriptor, CmArmMemoryRangeDescriptorInfoParser),
|
||||
CM_PARSER_ADD_OBJECT (EArmObjCpcInfo, CmArmCpcInfoParser),
|
||||
CM_PARSER_ADD_OBJECT (EArmObjPccSubspaceType0Info, CmArmPccSubspaceType0InfoParser),
|
||||
CM_PARSER_ADD_OBJECT (EArmObjPccSubspaceType1Info, CmArmPccSubspaceType1InfoParser),
|
||||
CM_PARSER_ADD_OBJECT (EArmObjPccSubspaceType2Info, CmArmPccSubspaceType2InfoParser),
|
||||
|
|
|
@ -463,38 +463,38 @@ The CM_OBJECT_ID type is used to identify the Configuration Manager
|
|||
| 20 | CMN 600 Info | |
|
||||
| 21 | Reserved Memory Range Node | |
|
||||
| 22 | Memory Range Descriptor | |
|
||||
| 23 | Continuous Performance Control Info | Move to Arch Common NS |
|
||||
| 24 | Pcc Subspace Type 0 Info | Move to Arch Common NS |
|
||||
| 25 | Pcc Subspace Type 1 Info | Move to Arch Common NS |
|
||||
| 26 | Pcc Subspace Type 2 Info | Move to Arch Common NS |
|
||||
| 27 | Pcc Subspace Type 3 Info | Move to Arch Common NS |
|
||||
| 28 | Pcc Subspace Type 4 Info | Move to Arch Common NS |
|
||||
| 29 | Pcc Subspace Type 5 Info | Move to Arch Common NS |
|
||||
| 30 | Embedded Trace Extension/Module Info | |
|
||||
| 31 | P-State Dependency (PSD) Info | Move to Arch Common NS |
|
||||
| 23 | Pcc Subspace Type 0 Info | Move to Arch Common NS |
|
||||
| 24 | Pcc Subspace Type 1 Info | Move to Arch Common NS |
|
||||
| 25 | Pcc Subspace Type 2 Info | Move to Arch Common NS |
|
||||
| 26 | Pcc Subspace Type 3 Info | Move to Arch Common NS |
|
||||
| 27 | Pcc Subspace Type 4 Info | Move to Arch Common NS |
|
||||
| 28 | Pcc Subspace Type 5 Info | Move to Arch Common NS |
|
||||
| 29 | Embedded Trace Extension/Module Info | |
|
||||
| 30 | P-State Dependency (PSD) Info | Move to Arch Common NS |
|
||||
| `*` | All other values are reserved. | |
|
||||
|
||||
#### Object ID's in the Arch Common Namespace:
|
||||
|
||||
| ID | Description | Comments |
|
||||
| ---: | :-------------------------- | :--- |
|
||||
| 0 | Reserved | |
|
||||
| 1 | Power Management Profile Info | |
|
||||
| 2 | Serial Port Info | |
|
||||
| 3 | Serial Console Port Info | |
|
||||
| 4 | Serial Debug Port Info | |
|
||||
| 5 | Hypervisor Vendor Id | |
|
||||
| 6 | Fixed feature flags for FADT | |
|
||||
| 7 | CM Object Reference | |
|
||||
| 8 | PCI Configuration Space Info | |
|
||||
| 9 | PCI Address Map Info | |
|
||||
| 10 | PCI Interrupt Map Info | |
|
||||
| 11 | Memory Affinity Info | |
|
||||
| 12 | Device Handle Acpi | |
|
||||
| 13 | Device Handle PCI | |
|
||||
| 14 | Generic Initiator Affinity Info | |
|
||||
| 15 | Low Power Idle State Info | |
|
||||
| 16 | Processor Hierarchy Info | |
|
||||
| 17 | Cache Info | |
|
||||
| `*` | All other values are reserved. | |
|
||||
| ID | Description | Comments |
|
||||
| ---: | :-------------------------- | :--- |
|
||||
| 0 | Reserved | |
|
||||
| 1 | Power Management Profile Info | |
|
||||
| 2 | Serial Port Info | |
|
||||
| 3 | Serial Console Port Info | |
|
||||
| 4 | Serial Debug Port Info | |
|
||||
| 5 | Hypervisor Vendor Id | |
|
||||
| 6 | Fixed feature flags for FADT | |
|
||||
| 7 | CM Object Reference | |
|
||||
| 8 | PCI Configuration Space Info | |
|
||||
| 9 | PCI Address Map Info | |
|
||||
| 10 | PCI Interrupt Map Info | |
|
||||
| 11 | Memory Affinity Info | |
|
||||
| 12 | Device Handle Acpi | |
|
||||
| 13 | Device Handle PCI | |
|
||||
| 14 | Generic Initiator Affinity Info | |
|
||||
| 15 | Low Power Idle State Info | |
|
||||
| 16 | Processor Hierarchy Info | |
|
||||
| 17 | Cache Info | |
|
||||
| 18 | Continuous Performance Control Info | |
|
||||
| `*` | All other values are reserved. | |
|
||||
|
||||
|
|
Loading…
Reference in New Issue