This patch provides the UI to support TLS auth configuration.
* EFI_SIGNATURE_LIST format is used for 'TlsCaCertificate'
variable. So, TLS supports multiple certificate configuration.
* The variable attribute is BS with NV, which only target at
preventing runtime phase attack.
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Cc: Long Qin <qin.long@intel.com>
Cc: Thomas Palmer <thomas.palmer@hpe.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
v3:
* Typo fix and code refine.
* Rename the internal macros and function:
TLS_INSTANCE_FROM_PROTOCOL_THIS -> TLS_INSTANCE_FROM_PROTOCOL
TLS_INSTANCE_FROM_CONFIGURATION_THIS -> TLS_INSTANCE_FROM_CONFIGURATION
TlsEcryptPacket -> TlsEncryptPacket
v2:
* Refine the TlsEcryptPacket/TlsDecryptPacket function
according the community feedback.
This patch is the implementation of EFI TLS Service Binding
Protocol, EFI TLS Protocol and EFI TLS Configuration Protocol
Interfaces.
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Cc: Long Qin <qin.long@intel.com>
Cc: Thomas Palmer <thomas.palmer@hpe.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
v2:
* Code refine and Typo fix:
TlsHandeAlert -> TlsHandleAlert
This patch is used to add new TlsLib library, which is wrapped
over OpenSSL. The implementation provides TLS library functions
for EFI TLS protocol and EFI TLS Configuration Protocol.
Cc: Ye Ting <ting.ye@intel.com>
Cc: Long Qin <qin.long@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Cc: Thomas Palmer <thomas.palmer@hpe.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com>
Reviewed-by: Qin Long <qin.long@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
This path is used to standardize TLS definitions from related
RFCs. Including TLS Cipher Suites, TLS Version, TLS Content Type
and TLS Record Header, etc.
Cc: Long Qin <qin.long@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Thomas Palmer <thomas.palmer@hpe.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com>
Reviewed-by: Qin Long <qin.long@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
This patch is used to add Tls.h and TlsConfig.h header
files to define EFI TLS Configuration Protocol,
EFI TLS Service Binding Protocol and
EFI TLS Configuration Protocol.
Cc: Long Qin <qin.long@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Thomas Palmer <thomas.palmer@hpe.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com>
Reviewed-by: Qin Long <qin.long@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
This commit refines the logic for HttpBootUintnToAscDecWithFormat and
PxeBcUintnToAscDecWithFormat. It avoids using the decrement operator '--'
for array index to prevent possible mis-reports by static code checkers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
This commit refines the logic for the CvtNum function. It avoids using the
decrement operator '--' for array index to prevent possible mis-reports by
static code checkers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
This commit rewrites the logic for NetblockChecksum. It processes the
checksum of the left-over byte first to prevent possible mis-reports by
static code checkers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
This commit refines the logic for InternalMemSetMem16|32|64 functions. It
avoids using the decrement operator '--' for array index to prevent
possible mis-reports by static code checkers.
Please note that those modified functions are only consumed within
MemoryLib by APIs SetMem16|32|64, and those APIs will handle the case when
the input number of bytes to set is 0. Hence, the behavior of APIs
SetMem16|32|64 is not changed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
This commit adds an addtional check in AsciiStrnCmp and StrnCmp. It
explicitly checks the end of the sting pointed by 'SecondString' to make
the code logic easier for reading and to prevent possible mis-reports by
static code checkers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
This commit refines the logic for AsciiStrnLenS and StrnLenS. It makes the
logic more straightforward to prevent possible mis-reports by static code
checkers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Add PcdCpuSmmStmExceptionStackSize/PcdCpuMsegSize prompt and help
string to uni file.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
This warning has been disabled for C file. To be same, it is also disabled
for CPP file.
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
Fix build warnings of "format ?%d? expects argument of type ?int?, but
argument 5 has type ?long unsigned int? [-Wformat=]" for BaseTools,
while using "gcc version 4.8.4 (Ubuntu 4.8.4-2ubuntu1~14.04.3)".
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Fix build warnings of "format not a string literal and no format
arguments [-Wformat-security]" for BaseTools, while using "gcc version
4.8.4 (Ubuntu 4.8.4-2ubuntu1~14.04.3)".
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
For variable name, it should contain lower case characters.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
The WindowsLike and PosixLike bin wrappers for GenDepex.py do not use
correct path. GenDepex.py is not in a GenDepex directory. Instead, it is
in the AutoGen directory.
Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=292
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This patch sets the normal OS buffer EfiLoaderCode/Data,
EfiBootServicesCode/Data, EfiConventionalMemory, EfiACPIReclaimMemory
to be not present after SmmReadyToLock.
To access these region in OS runtime phase is not a good solution.
Previously, we did similar check in SmmMemLib to help SMI handler
do the check. But if SMI handler forgets the check, it can still
access these OS region and bring risk.
So here we enforce the policy to prevent it happening.
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Add a new instances of the SmmCpuFeaturesLib that is used by
platforms to enable the SMI Transfer Monitor(STM) feature.
This new instance is in the same directory as the default
SmmCpuFeaturesLib instance in order to share source files.
The DSC file is updated to build both SmmCpuFeatureLib
instances and to build two versions of the PiSmmCpuDxeSmm
module using each of the SmmCpuFeatureLib instances.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Split the default implementation of the SmmCpuFeaturesLib
into two files to prepare for the addition of the STM
specific SmmCpuFeaturesLib implementation. The STM
specific implementation installs a different SMI entry
handler and initialize the MSEG specific MSR at the end
of SmmCpuFeaturesInitializeProcessor().
This patch does not introduce any functional changes
to the default implementation of the SmmCpuFeaturesLib.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* Add GUIDed HOB that described MSEG region in SMRAM
* Add SM Monitor Init Protocol
* Add PCD to configure size of SMM exception stack
* Add PCD to configure MSEG region size if it is not
described by the gMsegSmramGuid GUIDed HOB.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Add comments to describe fields of MSEG_HEADER and
add define values for the MonitorFeatures field.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
This patch remove the ASSERT when receive a DHCP packet large than the maximum
cache buffer size.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
This patch remove the ASSERT when receive a DHCP packet large than the maximum
cache buffer size.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
Move to the new non-discoverable device protocols for wiring the PCI based
EHCI controller driver to the non-discoverable EHCI controller found on the
OMAP 3530.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
https://bugzilla.tianocore.org/show_bug.cgi?id=176
Update CPUID leaf and sub-leaf indexes and structures as described by
Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 2A, September 2016, CPUID instruction.
Summary of incompatible changes:
1. Field name changes in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
Bit 12 has been renamed from 'PQM' to 'RDT_M' and bit 15 has been renamed
from 'PQE' to 'RDT_A'.
2. Stucture and filed name changes for 'CPUID Platform QoS Monitoring
Information' related definitions
Definition 'CPUID_PLATFORM_QOS_MONITORING' has been renamed to
'CPUID_INTEL_RDT_MONITORING'.
Definition 'CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF'.
Definition 'CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF'.
3. Stucture and filed name changes for 'CPUID Platform QoS Enforcement
Information' related definitions
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT' has been renamed to
'CPUID_INTEL_RDT_ALLOCATION'.
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF' has been renamed to
'CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF'.
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF'.
This commit also updates the relating codes in
UefiCpuPkg/Application/Cpuid to reflect the changes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
https://bugzilla.tianocore.org/show_bug.cgi?id=176
Update the MSR header file of Skylake processor according to Intel(R) 64
and IA-32 Architectures Software Developer's Manual, Volume 3, September
2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.
Summary of incompatible changes:
1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS has been renamed to
IA32_PERF_GLOBAL_STATUS
Typo 'STAUS' has been fixed in SDM.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
https://bugzilla.tianocore.org/show_bug.cgi?id=176
Update MSR header files of processors (excluding Goldmont and Skylake
processors) according to Intel(R) 64 and IA-32 Architectures Software
Developer's Manual, Volume 3, September 2016, Chapter 35
Model-Specific-Registers (MSR).
Summary of incompatible changes:
General:
1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header
files has been removed or renamed to IA32_PERF_GLOBAL_STATUS
Typo 'STAUS' has been fixed in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.
2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS)
in processor-specific header files have been removed or renamed to
IA32_MC{X}_{XXX} (like IA32_MC4_STATUS)
Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.
Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in
SDM are still kept in processor-specific header files.
HaswellMsr.h:
1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed
Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE'
in SDM.
Since the MSR definition is the same with architectural MSR, we remove it.
SandyBridgeMsr.h:
1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields
0:3
Bit description change from 'Core {X} select' to 'Slice {X} select' for
bit 0:3 in SDM.
SilvermontMsr.h:
1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed
Bit description for this MSR is totally changed in SDM, we modify the
structure definition to align with it.
XeonDMsr.h:
1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY
and MSR_PKG_C10_RESIDENCY have been removed
Those 3 MSRs are not defined for this processor in SDM, we remove them.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Jiaxin Wu
Hao Wu
Dandan Bi
Eric Dong
Liming Gao
Heyi Guo
Chan, Amy
Yonghong Zhu
Ruiyu Ni
Jiewen Yao
Michael Kinney
Fu Siyuan
Ard Biesheuvel
Zhang, Chao B