The issue with locating the expected interface and endpoint descriptors
arises because `configDesc` (USB_CONFIG_DESCRIPTOR) and `IfDesc`
(USB_INTERFACE_DESCRIPTOR) are incremented by structure size rather than
by actual descriptor length.
Specifically:
- `configDesc` should be incremented by its actual length.
- `IfDesc` should be incremented by its actual length.
This incorrect increment causes misalignment, preventing access to the
subsequent interface and endpoint descriptors.
[Suggested Solution]
Update the code to increment the pointers by the actual descriptor lengths,
ensuring proper access to all descriptors in the USB configuration.
Signed-off-by: Aniket Surekar <Aniket.Surekar@Dell.com>
According to UEFI spec 2.10 errata A section 7.4.6
"All events from the EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES and
EFI_EVENT_GROUP_EXIT_BOOT_SERVICES event notification groups as well
as events of type EVT_SIGNAL_EXIT_BOOT_SERVICES must be signaled
before ExitBootServices() returns EFI_SUCCESS. The events are only
signaled once even if ExitBootServices() is called multiple times."
So keep track of whether ExitBootServices() has been called, and signal
the event group EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES only the first
time around.
EFI_EVENT_GROUP_EXIT_BOOT_SERVICES will only be signalled if
ExitBootServices() is going to run to [successful] completion, after
which calling it a second time is not possible anyway. So for this case,
no special handling is needed.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
When booting at EL2, enable VHE if available so that the early ID map
can be enabled as well. This gets rid of any memory accesses (reads or
writes) before the MMU and caches are enabled.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
With mSecureHashAlgorithms being static this should not be
needed any more.
Suggested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
With mSecureHashAlgorithms being static this should not be
needed any more.
Suggested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Links from acpica.org are now redirected to the ACPICA overview page
on intel.com. Update the link so it goes to the 20200717 download page.
Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Check PcdConfidentialComputingGuestAttr instead of calling
MemEncryptSevIsEnabled() and MemEncryptTdxIsEnabled() to figure
whenever SEV or TDX is enabled.
This allows to remove the MemEncryptSevLib + MemEncryptTdxLib
dependencies.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Improve the formatting of the error message when GetVariable
fails: start the message with an upper-case character, and close the
quotes around the variable name.
Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
The Fedora 40 images uses gcc 14, includes libasan and
libubsan, clang, and some fixes and improvements.
See c98ff99762
Signed-off-by: Oliver Steffen <osteffen@redhat.com>
The BDF format for PCI initiators in the SRAT table is incorrect.
The format is not a UINT16 but specific bytes.
PCI Bus Number (Bits 7:0 of Byte 2)
PCI Device Number (Bits 7:3 of Byte 3)
PCI Function Number (Bits 2:0 of Byte 3)
REF: https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#device-handle-pci
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Intel's ACPICA download is no longer on acpica.org, but that site
redirects to pages on intel.com. Update the link to acpica.org to
the new ACPICA download page.
Microsoft's acpi.info no longer exists, so update the link to point to
Microsoft's ACPI compiler information page.
While here, update the nasm link from http to https.
Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Update Tpm12.h and Tpm20.h and not use c++ reserved keywords
operator and xor in C structures to support use of these
include files when building with a C++ compiler.
This patch removes the temporary use of anonymous unions and
warning 4201 disable for VS20xx tool chains to complete the
following field name changes:
* operator -> operator_
* xor -> xor_
NOTE: This is a non-backwards compatible change to Tpm12.h
and Tmp20.h. And consumers of these include files that access
the "operator" or "xor" fields must be updated.
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Change xor to xor_ to avoid C++ reserved work name collisions
when building with C++ compilers.
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Update Tpm12.h and Tpm20.h and not use c++ reserved keywords
operator and xor in C structures to support use of these
include files when building with a C++ compiler.
This patch temporarily introduces an anonymous union to add
operator_ and xor_ fields to support migration from the current
field names to the new field names.
Warning 4201 is disabled for VS20xx tool chains is a temporary
change to allow the use of anonymous unions.
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Links from acpica.org are now redirected to the ACPICA overview page
on intel.com. Update the link so it goes to the 20200517 download page.
Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4874
Question CheckBox, OneOf and Numeric can refer to Bit EFI VarStore.
CheckBox: data type is Boolean (1 byte),
Numeric/Oneof: data type is always UNIT32 for BIT VarStore,
When get default value for BIT VarStore, should return default value
with sizeof (UINT32) rather than the byte the bit width occupied.
Or incorrect default value will be used due to the size mismatch.
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
When updating memory attributes, if only access attributes are changed,
the default memory cache attribute is NULL and a CACHE_CC is added by
default.
Signed-off-by: Chao Li <lichao@loongson.cn>
BlockIo2 Read/Write/Flush APIs should signal the token's event when the
I/O operation completes, but the Emulator APIs do not. As a result, any
code that tries to implement async I/O will hang on emulator.
Both Windows and Unix emulator hosts work the same way:
- All I/O is completed synchronously.
- All I/O implementations contain the comment:
`// Caller is responsible for signaling EFI Event`
However, the protocol implementations do not signal the event, so the
event is never signalled.
Fix is to signal the event in the appropriate protocol implementations.
- If the host API returns success then the I/O is complete since it's
always synchronous.
- If there is a Token and Token->Event is not null and the I/O is
successful then the event should be signalled.
Signed-off-by: Doug Cook <idigdoug@gmail.com>
Introduce support for generating ACPI CPU SSDT table
for the X64 architecture.
Creates processor objects based on configuration data.
Cc: Sami Mujawar <Sami.Mujawar@arm.com>
Cc: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Updates X64 namespace object.
Updates the object parser.
Updates the Readme.
Cc: Sami Mujawar <Sami.Mujawar@arm.com>
Cc: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Currently, PciHostBridgeUtilityGetRootBridgesHostProvided allocates memory
for aperture structures without clearing memory. This causes garbage in
the Translation field, but the Base and Limit fields have the correct
values because they are copied from the HOST_BRIDGE_INFO fields in the
HardwareInfoPciHostBridgeHostBridgeHostBridgeGetApertures function.
RootBridge: PciRoot(0x0)
Support/Attr: 70069 / 70069
DmaAbove4G: No
NoExtConfSpace: No
AllocAttr: 3 (CombineMemPMem Mem64Decode)
Bus: 0 - 80 Translation=0
Io: 6000 - FFFF Translation=5E9EB018
Mem: 80000000 - DFFFFFFF Translation=0
MemAbove4G: 600000000000 - 7FFFFFFFFFFF Translation=0
PMem: FFFFFFFFFFFFFFFF - 0 Translation=0
PMemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
Signed-off-by: Alexander Gryanko <xpahos@gmail.com>
Since the pixiefail CVE fix the network stack requires a hardware
random number generator. This can currently be a modern CPU supporting
the RDRAND instruction or a virtio-rng device.
The latter is initialized during the BDS phase.
To ensure all depending (network) modules are also started, we need to
run the dispatcher once more after the device was initialized.
Without this, network boot is not available under certain hardware
configurations.
Fixes: 4c4ceb2ceb ("NetworkPkg: SECURITY PATCH CVE-2023-45237")
Analysed-by: Stefano Garzarella <sgarzare@redhat.com>
Suggested-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Oliver Steffen <osteffen@redhat.com>
StrSize() cannot return 0. As done in other packages, StrSize()
checks the length of the string doesn't exceed
PcdMaximumUnicodeStringLength. Add comments to make it more obvious.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4859
Reported-by: Tormod Volden <debian.tormod@gmail.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
The "Found ACPI table" messages are informative and don't indicate an
error, so reduce the debug level from DEBUG_ERROR to DEBUG_INFO.
Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
ArmVirtKvmTool might execute at EL2 when running under nested
virtualization, and in this case, it should not use HVC but SMC to
invoke PSCI and SMCCC services.
Like QEMU, kvmtool provides the PSCI conduit via a node in the FDT, and
as per the SMCCC, the PSCI conduit and the SMCCC conduit are guaranteed
to be the same. So switch to the ArmMonitorLib implementation that
selects the conduit based on this FDT node.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
The implementation of ArmMonitorLib that selects the conduit (SMC or
HVC) based on the PSCI FDT node is suitable for other VMMs as well, so
rename it more appropriately.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
HCR_EL2 may contain fields that should be preserved (such as E2H, which
may be RES1 for all intents and purposes other than reading back the
register). So preserve the existing value when setting the TGE bit.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
With VHE enabled, EL2 uses the EL2&0 translation regime, which is
compatible with the EL1&0 translation regime when it comes to the TCR
configuration register and the page table descriptor.
Given that some CPUs may have VHE force enabled when executing at EL2,
the MMU code needs to be able to deal with this even if it doesn't
enable VHE itself.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Remove the code path for execution at EL3, which just dumps an error.
None of the other code is remotely suitable for execution at EL3, and so
just ASSERT()'ing here is sufficient, and simplifies future changes
related to VHE.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
When VHE is enabled, some pre-existing timer system register specifiers
are redirected to the HYP timer. To access the conventional timer,
special aliases have to be used that end in _EL02.
These aliases are not understood by Clang's internal assembler, so use
the generic mnemonics instead.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Add definitions for the non-global page tables descriptor attribute, as
well as the E2H TCR bit, so that we can use them in the MMU code.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Gerd Hoffmann
Aniket_Surekar
Ard Biesheuvel
Chao Li
Oliver Steffen
Rebecca Cran
Ray Ni
Oliver Smith-Denny
Jeff Brasen
Michael D Kinney
Dandan Bi
Doug Cook (WINDOWS)
Abdul Lateef Attar
Alexander Gryanko
Yang Gang
Marc Chen
Pierre Gondois