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Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
The patch doesn't have functionality impact. It is just to make
VS2010/VS2012 happy.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
The patch adds support to certain devices that support PUIS (Power
up in Standby).
For those devices that supports SET_FEATURE spin up, SW needs to
send SET_FEATURE subcommand to spin up the devices.
For those devices that doesn't support SET_FEATURE spin up, SW needs
to send read sectors command to spin up the devices.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=699
Within function AhciModeInitialization(), left shift operations of 'BIT0'
in the following statements:
"if ((PortImplementBitMap & (BIT0 << Port)) != 0) {"
will incur possible out of range left shift when Port is 31, since
"1 << 31" is possible to exceed the range of type 'int' (signed).
According to the C11 spec, Section 6.5.7:
> 4 The result of E1 << E2 is E1 left-shifted E2 bit positions; vacated
> bits are filled with zeros. If E1 has an unsigned type, the value
> of the result is E1 * 2^E2 , reduced modulo one more than the
> maximum value representable in the result type. If E1 has a signed
> type and nonnegative value, and E1 * 2^E2 is representable in the
> result type, then that is the resulting value; otherwise, the
> behavior is undefined.
This commit explicitly cast 'BIT0' with UINT32 to resolve this issue.
Cc: Steven Shi <steven.shi@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
The SATA spec mandates that link detection by the PHY completes within
10 ms after receiving a reset signal. However, there is no obligation
to uphold this requirement at the driver end as strictly as we do, and
as it turns out, some combinations of host and device (e.g., Samsung
850 EVO connected to a LeMaker Cello) are only borderline compliant,
which means the device is not detected reliably.
So let's allow for a bit of margin, and increase the PHY detect timeout
value to 15 ms.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Star Zeng <star.zeng@intel.com>
According to AHCI Spec 1.3 GHC.AE bit description:
"The implementation of this bit is dependent upon the value of the
CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall
have a reset value of '0'. If CAP.SAM is '1', then AE shall be read-only
and shall have a reset value of '1'."
Being in AhciMode, for proper operation it is required, that GHC.AE bit
is always set, before any other AHCI registers are written to. Current
AhciMode implementation, both in AhciReset() and AhciModeInitialization()
functions, set GHC.AE bit only depending on 'CAP.SAM == 0' condition,
assuming (according to the AHCI spec), that otherwise it has to be set
anyway. It may however happen, that even if 'CAP.SAM == 1', GHC.AE
requires updating by software.
This patch enables in AhciMode setting GHC.AE in case its initial value
is '0'. It fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC
families. The change is transparent to all other platforms.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
AhciDumpPortStatus doesn't fully populate all the fields of
AtaStatusBlock after completing command execution, which may bring
issue if someone depends on the return status.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
It is enough to set PxCMD.FRE bit, which cause HBA to post received FISes
into the FIS receive area. According to AHCI Specification, only polling on
PxCMD.FRE to be cleared is necessary, when it is needeed to stop FIS engine
(eg. in order to change PxCMD.FB address).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
The Mantis ticket 1353 <https://mantis.uefi.org/mantis/view.php?id=1353>
and Mantis ticket 1472 <https://mantis.uefi.org/mantis/view.php?id=1472>
updated the description of the port multiplier port number parameter in
SATA Device Path Node and ATA Pass-Through Protocol.
Now, this parameter should be set to 0xFFFF instead of 0 to indicate that
an ATA device is directly attached on the controller port.
Please note that this is an incompatible change. The consumer of SATA
device path or ATA_PASS_THRU needs to re-examine its usage to follow UEFI
2.5 mantis 1353 and 1472.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Setting a bit in the PxSACT register for a command in the command list indicates
to the controller that the command list slot contains a native queued command (NCQ).
This can cause problems with some controllers (one such controller is the Marvell 9128).
Since NCQ commands are not used, don't set the PxACT register for commands issued.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Ruffin <chris.ruffin@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16536 6f19259b-4bc3-4df7-8a09-765794883524
Per AHCI 1.1 spec, AE bit of GHC register is read-only if CAP.SAM is 1
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16321 6f19259b-4bc3-4df7-8a09-765794883524
This way is used to avoid that the subsequent operations are treated as failure if the last operation is wrong.
Signed-off-by: Tian Feng <feng.tian@intel.com>
Reviewed-by: Sun Rui <rui.sun@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13663 6f19259b-4bc3-4df7-8a09-765794883524
1. move the non-blocking task related setting ahead to store the MapTable and PageCount in case there is a IO operation error happened then the error handler code could use those information to release the resource.
2. Enlarge the TPL protective area to make sure the simulative delay time is accurate when there is mixing usage of Non blocking and blocking I/O.
Signed-off-by: qianouyang
Reviewed-by: erictian
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12712 6f19259b-4bc3-4df7-8a09-765794883524
1. Boost IDE mode boot when slave device is absent.
2. Use D2H FIS to check if the PIO OUT/DMA IN/DMA OUT transfer is finished or error happened. ATA PIO IN has special check as it may just receive PIO SETUP FIS for success case.
3. Add command status register check for IDE DMA transfer.
4. ScsiDiskReadCapacity() in ScsiDisk should return EFI_SUCCESS if SENSE Data request is success.
Signed-off-by: erictian
Reviewed-by: rsun3
Reviewed-by: xdu2
Reviewed-by: mdkinney
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12658 6f19259b-4bc3-4df7-8a09-765794883524
GCC 4.6 generates a warning when a variable is set,
but never used.
Signed-off-by: jljusten
Reviewed-by: lgao4
Reviewed-by: erictian
Reviewed-by: rsun3
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12617 6f19259b-4bc3-4df7-8a09-765794883524
Liming Gao
Ruiyu Ni
Hao Wu
Ard Biesheuvel
Marcin Wojtas
Feng Tian
Jan D?bro?
Samer El-Haj-Mahmoud
Chris Ruffin
Reza Jelveh
Elvin Li
erictian
lgao4
qianouyang
jljusten
li-elvin