Commit Graph

10 Commits

Author SHA1 Message Date
Liming Gao 7367cc6c24 UefiCpuPkg: Clean up source files
1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
2018-06-28 11:19:53 +08:00
Eric Dong bc2300577f UefiCpuPkg: Enable Processor Trace feature.
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-08-04 12:26:44 +08:00
Eric Dong 3d6275c113 UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature.
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-08-04 08:49:05 +08:00
Marvin.Haeuser@outlook.com 91ec57c448 UefiCpuPkg/CpuCommonFeaturesLib: Fix the documentation of PpinSupport().
The documentation of PpinSupport() refers to 'Enhanced Intel
SpeedStep'. This patch fixes these referneces.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-08-03 09:05:47 +08:00
Eric Dong ee1d736a0a UefiCpuPkg CpuCommonFeaturesLib: Enable Ppin feature.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-07-20 14:11:15 +08:00
Eric Dong b1fe2029fa UefiCpuPkg CpuCommonFeaturesLib: Fix smx/vmx enable logic error.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed: Jeff Fan <jeff.fan@intel.com>
2017-07-12 08:51:08 +08:00
Jeff Fan 6661abb695 UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enable
Current X2APIC is enabled in MpInitLib (used by CpuMpPei and CpuDxe) to follow
SDM suggestion. That means we only enable X2APIC if we found there are any
initial CPU ID value >= 255.

This patch is to provide one chance for platform to enable X2APIC even there is
no any initial CPU ID value >= 255.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2017-05-27 13:29:38 +08:00
Jeff Fan 80c4b23638 UefiCpuPkg/CpuFeatures: Change files format to DOS
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-04-05 16:33:16 +08:00
Jeff Fan afc6201759 UefiCpuPkg/CpuCommonFeaturesLib: Fix case write issue
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-23 09:19:26 +08:00
Jeff Fan 0a70d1c304 UefiCpuPkg: Add NULL CPU Common Features Library instance
This NULL CPU common Features Library instance will register some CPU features
defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR).

Add PCD PcdCpuClockModulationDutyCycle and PcdIsPowerOnReset consumed by NULL
CPU Common Features Library instance.

v2:
  1. Using MSR_IA32_EFER to enable/disable NX feature instead of using
     MSR_IA32_MISC_ENABLE.
  2. Fix bug that SMX and VMX feature is swapped.

v3:
  1. Add AesniGetConfigData() to get current register state.

v5:
  Move MSR reading from AesniGetConfigData() to AesniSupport().

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:58 +08:00