According to the PCI spec, when software writes all-one to BAR for size probing,
the value read back should be 0b1...10...0 after masking the BAR type bits.
But in real world, it's possible that certain device returns 0b0...01...10...0
for MEM64 BAR size probing: some bits in the high 32bit may be 0.
PciBus driver has the code to handle such case. However, it doesn't handle the
case that the high 32bit is totally 0. The patch is to handle the special case.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18114 6f19259b-4bc3-4df7-8a09-765794883524
This is the legacy part of the old BdsDxe driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18112 6f19259b-4bc3-4df7-8a09-765794883524
This is the UI part of the old BdsDxe driver, also remove the legacy boot option related code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18111 6f19259b-4bc3-4df7-8a09-765794883524
Remove obsolete ARM and AARCH64 platforms so the maintainers can
focus on the ones that are still supported, which are:
- TC2 (ArmVExpress-CTA15-A7.dsc)
- Foundation model and Fast model emulators (ArmVExpress-FVP-AArch64.dsc)
- Juno (ArmJunoPkg/ArmJuno.dsc)
- Cortex-A15 MPcore RTSM (ArmVExpress-RTSM-A15_MPCore)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18110 6f19259b-4bc3-4df7-8a09-765794883524
The logic in an if statement in PciIo is too complex and hard to understand
and make VS2015 build failure. The fix simplifies the logic.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18109 6f19259b-4bc3-4df7-8a09-765794883524
This fix is used to solve VS2015 warning "local variable is not initialized before use"
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18108 6f19259b-4bc3-4df7-8a09-765794883524
DHCP4 service allows only one of its children to be configured
in the active state,If the DHCP4 D.O.R.A started by IP4 auto
configuration and has not been completed, the Dhcp4 state machine
will not be in the right state for the PXE to start a new round
D.O.R.A., so we need to switch it's policy to static.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18107 6f19259b-4bc3-4df7-8a09-765794883524
CapsuleX64 is for 64bits capsule data access in PEI phase,
it is only needed for X64 DXE build.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Tim He <tim.he@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18106 6f19259b-4bc3-4df7-8a09-765794883524
It was forgotten to be included in MdeModulePkg.dsc when created.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18105 6f19259b-4bc3-4df7-8a09-765794883524
DHCP4 service allows only one of its children to be configured
in the active state,If the DHCP4 D.O.R.A started by IP4 auto
configuration and has not been completed, the Dhcp4 state machine
will not be in the right state for the PXE to start a new round D.O.R.A.
so we need to switch it's policy to static.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18104 6f19259b-4bc3-4df7-8a09-765794883524
Since it is arguably incorrect to infer the GIC revision from CPU
ID and GIC feature registers on platforms that describe the GIC in
the device tree, this implements the library class ArmGicArchLib
tailored for such platforms.
The supported GIC revision is retrieved from the dynamic PCD that
is set based on the GIC DT node.
This means this library can only execute post DXE core, but this is
not a problem for any of the virt platforms.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18102 6f19259b-4bc3-4df7-8a09-765794883524
In order to allow a ArmGicArchLib to be implemented that returns
the supported GIC revision based on the device tree, add handling
to VirtFdtDxe to record the GIC revision at DT parsing time.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18101 6f19259b-4bc3-4df7-8a09-765794883524
Instead of inferring the GIC revision from the CPU id registers
and the presence/availability of the system register interface
upon each invocation, move the logic to a constructor and cache
the result.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18100 6f19259b-4bc3-4df7-8a09-765794883524
Clone ArmGicArchLib into a SEC phase specific ArmGicArchSecLib
so that we can modify the former in a subsequent patch to cache
the GIC revision in a global variable.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18099 6f19259b-4bc3-4df7-8a09-765794883524
The current implementation of ArmGicGetSupportedArchRevision ()
that is used by all ARM platforms is entirely stateless (in order
to support being executed from flash) so it needs to interrogate
the hardware for the supported GIC revision upon each invocation.
However, this statelessness is only needed for SEC type modules;
in all other cases, we could easily determine the GIC revision once,
and store the result in a global variable.
In preparation of having separate early and normal versions, this patch
introduces the ArmGicArchLib library class and default implementation,
and moves the existing ArmGicGetSupportedArchRevision () into it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18098 6f19259b-4bc3-4df7-8a09-765794883524
Before splitting off ArmGicArchLib and moving it out of
ArmPkg/Drivers/ArmGic into ArmPkg/Library, make sure that the
GIC specific declarations it depends on are not hidden away in
local headers "GicV2/GicV2Lib.h" and "GicV3/GicV3Lib.h".
So merge them with <Library/ArmGicLib.h>. This is entirely
appropriate, since this is not a header that declares a public
interface into ArmGicLib, but defines implementation internals.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18097 6f19259b-4bc3-4df7-8a09-765794883524
The FSP API is always 32bit, but FspNotifyDxe might load to >4G memory. In order to make thunk work, we need reload FspNotifyDxe to <4G memory.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18094 6f19259b-4bc3-4df7-8a09-765794883524
Add a new module MemoryOverwriteRequestControlLock to register VarCheck handler to enforce MorLock Policy.
Only SMM version is added because MOR is only supported in SMM variable case.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Chao Zhang" <chao.b.zhang@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18092 6f19259b-4bc3-4df7-8a09-765794883524
No TPM2 is considered as valid case. For example, a platform may only have TPM1.2, without TPM2.0 So this is NOT an ERROR message, but more an INFO message.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Chao Zhang" <chao.b.zhang@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18091 6f19259b-4bc3-4df7-8a09-765794883524
The keyword with value TRUE OR FALSE is used to
indicate whether the FV UI name is included in
FV EXT header as a entry or not.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yingke Liu <yingke.d.liu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18090 6f19259b-4bc3-4df7-8a09-765794883524
GLOBAL_REMOVE_IF_UNREFERENCED means __declspec(selectany) for MS tool
chain IA32/X64 build.
According to MSDN, "selectany" would tell the compiler that the declared
global data item (variable or object) is a pick-any COMDAT (a packaged
function). At link time, if multiple definitions of a COMDAT are seen,
the linker picks one and discards the rest.
So we have to remove GLOBAL_REMOVE_IF_UNREFERENCED key word from two global
variable's extern definitions of .h file as we have used this keyword in
.c file, otherwise the MS tool chain would pick the definitions in .h file
and treat it as uninitialized data to generate full-0 content for these two
global variables.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18088 6f19259b-4bc3-4df7-8a09-765794883524
to instead of AllocatePool() to ensure the data is clean for
the following consumption.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18087 6f19259b-4bc3-4df7-8a09-765794883524
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qiu Shumin <shumin.qiu@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18084 6f19259b-4bc3-4df7-8a09-765794883524
To prevent double padding of XIP modules leading to excessive
waste of FV space, try to adjust existing padding rather than
adding more.
Instead of adding a pad file to the FV to line up an FFS file that
itself may contain padding to line up the payload, try to find a
dedicated padding section inside the FFS, and reduce its size to
place all subsequent aligned FFS section at their respective minimum
alignments.
When using 4 KB section alignment (which is required on AARCH64 in
some cases), this will save 4 KB for each XIP module.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Yingke Liu <yingke.d.liu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18080 6f19259b-4bc3-4df7-8a09-765794883524
Instead of using an anonymous section of type EFI_SECTION_RAW to pad
out the first aligned FFS section to its required alignment, use a
section with a dedicated GUID if the size of the padding permits it.
This allows for more flexibility when placing such FFS images in a
firmware volume, because we will now be able to remove padding rather
than add more, by shrinking the size of this section instead of
padding out the start of the FFS image to file alignment.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Yingke Liu <yingke.d.liu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18079 6f19259b-4bc3-4df7-8a09-765794883524
The secondary header (not the DOS header) of a PE/COFF binary
does not reside at a fixed offset. Instead, its offset into the
file is recorded in the DOS header.
This gives us the flexibility to move it, along with the section
headers, to right before the first section if there is considerable
space before it, i.e., when the PE/COFF file alignment is substantially
larger than the size of the header.
Since the PE/COFF to TE conversion replaces everything before the
section headers with a simple TE header, this change removes all
the header padding from such images, leading to smaller files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Yingke Liu <yingke.d.liu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18078 6f19259b-4bc3-4df7-8a09-765794883524
In order to reduce the memory footprint of PE/COFF images when
using large values for the PE/COFF section alignment, move the
contents of the .debug section to data, and point the debug data
directory entry to it. This allows us to drop the .debug section
entirely, as well as any associated rounding. Since our .debug
section only contains the filename of the ELF input image, the
penalty of keeping this data in a non-discardable section is
negligible.
Note that the PE/COFF spec v6.3 explicitly mentions that this is
allowed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Yingke Liu <yingke.d.liu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18077 6f19259b-4bc3-4df7-8a09-765794883524
When load default value or save changes will pop up message box to let user
confirm,Y means confirm and N means ignore,now add Esc key with the
same function of N key.And change the content of pop up message in .uni file,
now will display "Press 'Y' to confirm, 'N'/'ESC' to ignore."
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18076 6f19259b-4bc3-4df7-8a09-765794883524
Enhance the setupbrowserdxe to output debug message when DisplayEngineDxe is
not installed and this will be easy for user to find the reason why can not
enter Setup page.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18075 6f19259b-4bc3-4df7-8a09-765794883524
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc doesn't use any X64
modules, so it should not specify the X64 architecture.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18073 6f19259b-4bc3-4df7-8a09-765794883524
Reduce reserved memory consumption by page table buffer,
then OS can have more available memory to use.
Take PhysicalAddressBits = 48 and 2MB page granularity as example,
1:1 Virtual to Physical identity mapping page table buffer needs to be
((512 + 1) * 512 + 1) * 4096 = 1075843072 bytes = 0x40201000 bytes.
The code is updated to only allocate 2 pages (1G page enabled) or
6 pages for 4G page table, and 8 extra pages to handles > 4G request
by page fault.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18070 6f19259b-4bc3-4df7-8a09-765794883524
We are going to reduce reserved memory consumption by page table buffer,
then OS can have more available memory to use.
Take PhysicalAddressBits = 48 and 2MB page granularity as example,
1:1 Virtual to Physical identity mapping page table buffer needs to be
((512 + 1) * 512 + 1) * 4096 = 1075843072 bytes = 0x40201000 bytes.
The code is updated to build 4G page table by default and only use 8 extra
pages to handles > 4G request by page fault.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18069 6f19259b-4bc3-4df7-8a09-765794883524
Reduce reserved memory consumption by page table buffer,
then OS can have more available memory to use.
Take PhysicalAddressBits = 48 and 2MB page granularity as example,
1:1 Virtual to Physical identity mapping page table buffer needs to be
((512 + 1) * 512 + 1) * 4096 = 1075843072 bytes = 0x40201000 bytes.
When BIOS does not support long mode waking vector, only allocate
2 pages (1G page enabled) or 6 pages for 4G page table, and 8 extra
pages to handles > 4G request by page fault.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18068 6f19259b-4bc3-4df7-8a09-765794883524
We are going to reduce reserved memory consumption by page table buffer,
then OS can have more available memory to use.
Take PhysicalAddressBits = 48 and 2MB page granularity as example,
1:1 Virtual to Physical identity mapping page table buffer needs to be
((512 + 1) * 512 + 1) * 4096 = 1075843072 bytes = 0x40201000 bytes.
Current BootScriptExecutorDxe handles > 4G request by page fault because
S3ResumePeim only builds 4G page table when long mode waking vector is
not needed, but BootScriptExecutorDxe still assume the page table buffer for
page table is at 1:1 Virtual to Physical identity mapping.
To reduce reserved memory consumption, the code is updated to only use
8 extra pages to handles > 4G request by page fault.
Another, when both BIOS and OS wants long mode waking vector,
S3ResumePei should have established 1:1 Virtual to Physical identity mapping
page table for ACPI spec requirement, so no need to hook page fault handler.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18067 6f19259b-4bc3-4df7-8a09-765794883524
Fix an error which leads the building process crashes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: fanwang2 <fan.wang@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18066 6f19259b-4bc3-4df7-8a09-765794883524
As variable HEADER_ALIGNMENT = 4, the MonotonicCount in
AUTHENTICATED_VARIABLE_HEADER may be not UINT64 aligned,
so go to use ReadUnaligned64() to ensure read data correctly.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18064 6f19259b-4bc3-4df7-8a09-765794883524
For AARCH64, do not define a memcpy function in stdlib because it is
already defined in CompilerIntrinsicsLib.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-by: Daryl McDaniel <edk2-lists@mc2research.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18063 6f19259b-4bc3-4df7-8a09-765794883524
When there are multiple network boot options, user will see multiple
"UEFI Network" boot options. It's hard to distinguish them using the
description.
The patch enhances the boot option generation logic to append " 2"
/" 3"/" 4"/... number suffix to the non-first network boot options.
So the 2nd one becomes "UEFI Network 2".
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18062 6f19259b-4bc3-4df7-8a09-765794883524
Ruiyu Ni
Eric Dong
Ard Biesheuvel
Michael D Kinney
Zhang Lubo
Star Zeng
Jaben Carsey
Laszlo Ersek
Yao, Jiewen
Yingke Liu
Chao Zhang
Feng Tian
Qiu Shumin
Dandan Bi
Jordan Justen
fanwang2
Scott Duplichan