REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1166
Visual Studio 2012 will complain uninitialized variable, StackBase,
in the CpuPaging.c. This patch adds code to init it to zero and
ASSERT check against 0. This is enough since uninit case will only
happen during retrieving stack memory via gEfiHobMemoryAllocStackGuid.
But this HOB will always be created in advance.
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This feature is the same as Stack Guard enabled in driver CpuDxe but
applies to PEI phase. Due to the specialty in PEI module dispatching,
this driver is changed to do the actual initialization in notify
callback of event gEfiPeiMemoryDiscoveredPpiGuid. This can let the
stack guard apply to as most PEI drivers as possible.
To let Stack Guard work, some simple page table management code are
introduced to setup Guard page at base of stack for each processor.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: "Ware, Ryan R" <ryan.r.ware@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Currently, the SecPlatformInformation2 PPI is installed when either
there is none present or the present one doesn't lack data.
Update the logic to only install the SecPlatformInformation2 PPI when
it's not already installed so that an up-to-date PPI remains the only
one and unchanged.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Build gEfiSecPlatformInformation2PpiGuid GUIDed-HOB to store all CPU BIST data
that could be used not only by SecPlatformInformation2(), but also by CPU MP Dxe
driver to get CPU BIST data.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
ProcessorInfo.ProcessorId is UINT64 type even it's valid value is UINT32. Use %x
only output the low 4 bytes and keep the high 4 bytes in stack that will be
output as the second parameter BistData. Typecast ProcessorInfo.ProcessorId to
UINT32 could make BistData output correctly.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
Consume MP initialize library to produce CPU MP PPI, it could simply the code.
Add STATIC for some internal functions to avoid build issue with the same
functions name in PeiMpInit instance. They will be removed by the next patch.
v4:
1. Update BistData type from UINT32 to EFI_HEALTH_FLAGS.
v3:
1. Rename MpInitLibSwitchBSP to MpInitLibSwitchBSP
2. Add PeiMpInitLib.inf in DSC file
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
#define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE
defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it
and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h.
Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined
in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and
update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from
ArchitecturalMsr.h.
v5:
1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Remove Pmode(Entry)Offset/Lmode(Entry)Offset and use unified Mode(Entry)Offset
to clean up the definition of MP_ASSEMBLY_ADDRESS_MAP and MP_CPU_EXCHANGE_INFO.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Do not load the new GDT table and just to use the exiting BSP's GDT table set up
by SEC phase.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode
MACROs for x64 arch. Switch AP from real mode to long mode directly, so needn't
the CS/DS of protected mode.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode
MACROs.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Added CodeSegment and DataSegment fields in MP_CPU_EXCHANGE_INFO. They are set
to the values of current BSP's CS and DS.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Verification microcode signature is one enhancement and not one requirement from
IA32 SDM. This update is just to dump debug message instead of ASSERT() if the
updated microcode signature does not match the loaded microcode signature.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Actually, there is only one microcode region in platform. If microcode has been
loaded, its signature will not be zero and should be loaded successfully.
We needn't to check microcode region and load microcode again. This update is to
skip checking/loading microcode if current microcode signature is not zero.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
- becasue to because
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
If ApLoopMode is set to ApInMwaitLoop, AP will be placed into C-State by mwait
instruction. BSP will wakeup AP by write start-up signal in monitor address.
However, AP maybe waken by SMI/NMI/MCE and other condition. On this case, AP
will check if BSP wants to wakeup itself really. If not, AP will continue to
execute mwait to C-State.
One potential issue: BSP may not recognize AP was wakeup from C-State by other
event and BSP still writes start-up signal to wakeup AP. But AP does not aware
it and still execute mwait instruction to C-State. So, AP cannot be wakeup on
this case.
This fix is let AP to clear start-up signal when it really is wakeup to execute
AP function. And BSP will write start-up signal till AP clears it.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Current implementation only loads the latest revision if there is no microcode
loaded. Per IA32 User Manual, we should load the newer revision by comparing
the existing microcode loaded with the updating revision.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
If ApLoopMode is ApInHltLoop, BSP will send INIT-SIPI-SIPI to wake up APs.
If ApLoopMode is ApInMwaitLoop or ApInRunLoop, BSP will write one semaphore to
wake up APs.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19346 6f19259b-4bc3-4df7-8a09-765794883524
After AP function is executed, we will place AP in proper loop mode. Because AP
maybe waken up by SMI or other reasons. We need to read signature in monitor
buffer to check if APs is waken up by BSP. If it is not waken up by BSP, we will
continue to place them into proper loop mode.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19345 6f19259b-4bc3-4df7-8a09-765794883524
Get AP loop mode to prepare for the monitor buffer required for ApInMwaitLoop
and ApInRunLoop.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19344 6f19259b-4bc3-4df7-8a09-765794883524
Add GetApLoopMode() that will get PCD PcdCpuApLoopMode firstly. If it is
ApInMwaitLoop, we will check if MONITOR/MWAIT feature supported by CPUID. If
MONITOR/MWAIT feature is not supported, force AP loop mode to ApInHltLoop.
GetApLoopMode() also return the largest line size required.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19343 6f19259b-4bc3-4df7-8a09-765794883524
Packing alignment for MP_CPU_EXCHANGE_INFO should be 1. This should be typo when
check-in CpuMpPei driver. IA32 arch MP_CPU_EXCHANGE_INFO is luckly pack(1). It
leads CpuMpPei x64 version hung.
Contributed-under: TianoCore Contribution Agreement 1.0
Reported-by: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19340 6f19259b-4bc3-4df7-8a09-765794883524
To convert these files I ran:
$ python3 BaseTools/Scripts/ConvertUni.py UefiCpuPkg
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19264 6f19259b-4bc3-4df7-8a09-765794883524
PeiStartupAllAPs()/PeiStartupThisAP() will send INIT-SIPI-SIPI to wakeup APs to
execute AP function. However, some registers will be reset after APs received
INIT IPI. We need to restore some registers (For example, CRx/DRx) manually
after APs wakeup.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19089 6f19259b-4bc3-4df7-8a09-765794883524
Save BSP's volatile register and sync CRx register to APs when AP 1st wake up.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19088 6f19259b-4bc3-4df7-8a09-765794883524
Add CPU_VOLATILE_REGISTERS definitions for CRx and DRx required to be restored
after APs received INIT IPI.
Add worker functions SaveVolatileRegisters()/RestoreVolatileRegisters() used to
save/restore CRx and DRx. It also check if Debugging Extensions supported or
not.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19086 6f19259b-4bc3-4df7-8a09-765794883524
Current implementation only exchanges the APIC ID and BIST, this updating is to
exchange all CPU data.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19085 6f19259b-4bc3-4df7-8a09-765794883524
If x2APIC flag is set, enable x2APIC mode on all APs and BSP. Before we wakeup
APs to enable x2APIC mode, we should wait all APs have finished initialization.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18934 6f19259b-4bc3-4df7-8a09-765794883524
If there are any logical processor reporting an APIC ID of 255 or greater, set
X2ApicEnable flag.
GetInitialApicId() will return x2APIC ID if CPUID leaf B supported.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18933 6f19259b-4bc3-4df7-8a09-765794883524
Move CPUID related defines from LocalApic.h to Cpuid.h
Update LocalApicLib instances to include Cpuid.h
Update CpuMpPei module to include Cpuid.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18633 6f19259b-4bc3-4df7-8a09-765794883524
Only perform AP detection if PcdCpuMaxLogicalProcessorNumber > 1
Only free AP related structures of they were allocated
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18629 6f19259b-4bc3-4df7-8a09-765794883524
CpuData buffer should be located in allocated buffer instead of at end of
WakeupBuffer.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18550 6f19259b-4bc3-4df7-8a09-765794883524
CPU Healthy state maybe changed by software. We should return Healthy state
from Healthy bit instead of from CPU BIST hardware information.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18374 6f19259b-4bc3-4df7-8a09-765794883524
Michael D Kinney
Jian J Wang
Marvin H?user
Liming Gao
Eric Dong
Jeff Fan
Giri P Mudusuru
Laszlo Ersek
Jordan Justen