Some missing files from the initial AArch64 commit.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14488 6f19259b-4bc3-4df7-8a09-765794883524
the PCI Bus driver through the function call NotifyPhase().
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14483 6f19259b-4bc3-4df7-8a09-765794883524
while MonthNo is the month of the year, so tm_mon should be MonthNo-1.
Similarly, tm_mday is the day of the month, and DayNo is the number
of days since the first day of the month. Assigning DayNo+1 to
tm_mday to fit the definition.
This commit also corrected miscalculated MonthNo and DayNo for the
first day of the month. (Thanks to Laszlo Ersek!)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Ching-Pang Lin <glin@suse.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Long Qin <qin.long@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14481 6f19259b-4bc3-4df7-8a09-765794883524
The GIC CPU Id (the GIC CPU interface the CPU is connected to) can be retrieved by reading the first
registers of the GIC CPU Target Registers.
The first GIC Distributor Target registers correspond to the SGIs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14479 6f19259b-4bc3-4df7-8a09-765794883524
This function is exposed by the MemoryAllocationLib header.
A dummy FreePages() function has been added to fix modules depending on
this library and this function.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14478 6f19259b-4bc3-4df7-8a09-765794883524
The idea is to remove the PCD PcdGicPrimaryCoreId to make the port easier (and also to allow changing
the primary boot CPU without adding more platform specific code to UEFI).
There is a risk the mailboxes contain garbage at boot time. But it should be easy enough to clear the
mailboxes when starting UEFI to workaround this limitation.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14477 6f19259b-4bc3-4df7-8a09-765794883524
Route both the setting and restoring of cacheability through DXE Services/GCD
and stop using the CPU AP directly.
The patch also removes all references to the CPU AP which eliminates the need
for a library constructor.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Senthil Ramakrishnan <senthil.ramakrishnan@hp.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14468 6f19259b-4bc3-4df7-8a09-765794883524
2. Remove the #defines and add the extern declarations for gEfiDebugPortVariableGuid and gEfiDebugPortDevicePathGuid.
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: michael.d.kinney@intel.com
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14465 6f19259b-4bc3-4df7-8a09-765794883524
1. The signature of working block header needs to be updated to gEdkiiWorkingBlockSignatureGuid because FTW write header and record has be updated and exposed to support crossing archs.
2. PEI variable has been updated to depend on FaultTolerantWritePei to robustly handle crashes during Reclaim(), so add FaultTolerantWritePei.inf in *.dsc and *.fdf.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14457 6f19259b-4bc3-4df7-8a09-765794883524
1. The signature of working block header needs to be updated to gEdkiiWorkingBlockSignatureGuid because FTW write header and record has be updated and exposed to support crossing archs.
2. PEI variable has been updated to depend on FaultTolerantWritePei to robustly handle crashes during Reclaim(), so add FaultTolerantWritePei.inf in *.dsc and *.fdf.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14456 6f19259b-4bc3-4df7-8a09-765794883524
PEI variable implementation checks only the variable header signature for validity. This does not seem robust if system crash occurred during previous Reclaim() operation. If the crash occurred while FTW was rewriting the variable FV, the signature could be valid even though the rest of the FV isn't valid.
Solution: PEI variable and early phase(before FTW protocol ready) of DXE variable can check the FTW last write status provided by FaultTolerantWritePei and determine if all or partial variable data has been backed up in spare block, and then use the backed up data.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14455 6f19259b-4bc3-4df7-8a09-765794883524
PEI variable implementation checks only the variable header signature for validity. This does not seem robust if system crash occurred during previous Reclaim() operation. If the crash occurred while FTW was rewriting the variable FV, the signature could be valid even though the rest of the FV isn't valid.
Solution: Add a FaultTolerantWritePei driver to check and provide the FTW last write status, then PEI variable and early phase(before FTW protocol ready) of DXE variable can check the status and determine if all or partial variable data has been backed up in spare block, and then use the backed up data.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14454 6f19259b-4bc3-4df7-8a09-765794883524
ARM Versatile Express TC2 Core Tile has two profiles: the 1GB DRAM core tile or
the 2GB DRAM core tile profiles.
By default UEFI assumes, it is the 1GB core tile. In case of 2GB DRAM it declares
this additional 1GB resource system memory to UEFI. But the previous code did
not map this memory in the MMU Page Table.
So, the memory was allocatable by UEFI modules, but was not accessible by the CPU
(because not mapped).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Leif Lindholm <Leif.Lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14449 6f19259b-4bc3-4df7-8a09-765794883524
The UEFI specification mandates that software uses the DescriptorSize returned
by the GetMemoryMap() function to find the start of each EFI_MEMORY_DESCRIPTOR
in the MemoryMap array. This allows for future expansion of the EFI_MEMORY_DESCRIPTOR.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14447 6f19259b-4bc3-4df7-8a09-765794883524
This creates a new parameter to this shell implementation “_exit” that causes the shell to automatically exit after running the initial specified command line. This also automatically uses that command in the Execute() API.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: jaben carsey <jaben.carsey@intel.com>
Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hp.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14444 6f19259b-4bc3-4df7-8a09-765794883524
This is required when recursively removing directories with files on file systems other than the current one.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey <Jaben.carsey@intel.com>
Reviewed-by: Eugene Cohen <eugene@hp.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14441 6f19259b-4bc3-4df7-8a09-765794883524
Harry Liebel
Jaben Carsey
Olivier Martin
Gary Ching-Pang Lin
Ruiyu Ni
Eric Dong
Eugene Cohen
Liming Gao
Star Zeng
Fu Siyuan
Feng Tian
Ari Zigler
Yu Pei