Commit Graph

103 Commits

Author SHA1 Message Date
Star Zeng 27bf6712b4 IntelSiliconPkg VTdDxe: Report status code for VTd error
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1273

Current code only uses DEBUG() for VTd error.
This patch updates to also report status code for VTd error.

Test done:
Created case that has VTd error and confirmed the error
status code could be reported as expected.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-10-25 11:50:49 +08:00
Star Zeng 8c09f30010 IntelSiliconPkg VTdDxe: Option to force no early access attr request
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1272

To have high confidence in usage for platform, add option (BIT2 of
PcdVTdPolicyPropertyMask) to force no IOMMU access attribute request
recording before DMAR table is installed.

Check PcdVTdPolicyPropertyMask BIT2 before RequestAccessAttribute()
and ProcessRequestedAccessAttribute(), then RequestAccessAttribute(),
ProcessRequestedAccessAttribute() and mAccessRequestXXX variables
could be optimized by compiler when PcdVTdPolicyPropertyMask BIT2 = 1.

Test done:
1: Created case that has IOMMU access attribute request before DMAR
   table is installed, ASSERT was triggered after setting
   PcdVTdPolicyPropertyMask BIT2 to 1.

2. Confirmed RequestAccessAttribute(), ProcessRequestedAccessAttribute()
   and mAccessRequestXXX variables were optimized by compiler after
   setting PcdVTdPolicyPropertyMask BIT2 to 1.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-10-25 11:50:43 +08:00
Star Zeng 74bdd03ead IntelSiliconPkg IntelVTdDxe: Use new EfiLocateFirstAcpiTable()
https://bugzilla.tianocore.org/show_bug.cgi?id=967
Request to add a library function for GetAcpiTable() in order
to get ACPI table using signature as input.

After evaluation, we found there are many duplicated code to
find ACPI table by signature in different modules.

This patch updates IntelVTdDxe to use new
EfiLocateFirstAcpiTable() and remove the duplicated code.

Cc: Younas khan <pmdyounaskhan786@gmail.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-09-27 14:25:33 +08:00
Star Zeng b06dfd40bb IntelSiliconPkg IntelVTdDxe: Check HeaderType if func 0 is implemented
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1169

Current code checks HeaderType of Function 0 even Function 0 is not
implemented. HeaderType value will be 0xFF if Function 0 is not
implemented, then MaxFunction will be set to PCI_MAX_FUNC + 1.

The code can be optimized to only check HeaderType if Function 0 is
implemented.

Test done:
With this patch, the result is same with the result after the patch at
https://lists.01.org/pipermail/edk2-devel/2018-September/029623.html.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Tomson Chang <tomson.chang@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-09-17 09:17:58 +08:00
Star Zeng e69d7e99e7 IntelSiliconPkg IntelVTdDxe: Optimize when func 0 is not implemented
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1169

PCI spec:
They are also required to always implement function 0 in the device.
Implementing other functions is optional and may be assigned in any
order (i.e., a two-function device must respond to function 0 but
can choose any of the other possible function numbers (1-7) for the
second function).

This patch updates ScanPciBus() to not scan other functions if
function 0 is not implemented.

Test done:
Added debug code below in the second loop of ScanPciBus(),
compared the debug logs with and without this patch, many
non-0 unimplemented functions are skipped correctly.

  DEBUG ((
    DEBUG_INFO,
    "%a() B%02xD%02xF%02x VendorId: %04x DeviceId: %04x\n",
    __FUNCTION__,
    Bus,
    Device,
    Function,
    VendorID,
    DeviceID
    ));

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Tomson Chang <tomson.chang@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-09-17 09:17:42 +08:00
Chen A Chen 6861b0fe72 IntelSiliconPkg: Removing ipf which is no longer supported from edk2.
Removing rules for Ipf sources file:
* Remove the source file which path with "ipf" and also listed in
  [Sources.IPF] section of INF file.
* Remove the source file which listed in [Components.IPF] section
  of DSC file and not listed in any other [Components] section.
* Remove the embedded Ipf code for MDE_CPU_IPF.

Removing rules for Inf file:
* Remove IPF from VALID_ARCHITECTURES comments.
* Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section.
* Remove the INF which only listed in [Components.IPF] section in DSC.
* Remove statements from [BuildOptions] that provide IPF specific flags.
* Remove any IPF sepcific sections.

Removing rules for Dec file:
* Remove [Includes.IPF] section from Dec.

Removing rules for Dsc file:
* Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC.
* Remove any IPF specific sections.
* Remove statements from [BuildOptions] that provide IPF specific flags.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chen A Chen <chen.a.chen@intel.com>
Reviewed-by: <Jiewen.yao@intel.com>
2018-09-13 13:12:02 +08:00
Liming Gao ca79bab7af IntelSiliconPkg: Clean up source files
1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
2018-06-28 11:19:44 +08:00
Star Zeng 8653ea2088 IntelSiliconPkg IntelVTdDxe: Fix incorrect code to clear VTd error
According to VTd spec, Software writes the value read from this
field (F) to Clear it. But current code is using 0 to clear the
field, that is incorrect.

And R_FSTS_REG register value clearing should be not in the for loop.

Without this patch, we will see same VTd error message appears again
and again after it occurs first time.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-06-06 12:46:43 +08:00
Star Zeng e91797885a IntelSiliconPkg MicrocodeUpdateDxe: Honor FIT table
It is the second step for
https://bugzilla.tianocore.org/show_bug.cgi?id=540.

V2: Use error handling instead of ASSERT for FIT table checking result.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-05-09 16:27:30 +08:00
Star Zeng 1779cf40c0 IntelSiliconPkg MicrocodeUpdate: Fix typo EFI_SECURITY_VIOLATIO
Fix typo EFI_SECURITY_VIOLATIO to EFI_SECURITY_VIOLATION.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-04-25 16:36:43 +08:00
Jiewen Yao 8d8c487fb9 IntelSiliconPkg/Vtd: Add more debug info.
Add more debug info for reason code.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-03-20 08:51:54 +08:00
Jiewen Yao 224f87932d IntelSiliconPkg/Vtd: Add missing dump in ExtContext.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-03-12 13:17:15 +08:00
Jiewen Yao 6cea3c1b51 IntelSiliconPkg/Vtd: Add DMA_CTRL_PLATFORM_OPT_IN_FLAG dump
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-03-12 13:17:14 +08:00
Jiewen Yao 6d2d2e6e5b IntelSiliconPkg/Vtd: Add MapHandleInfo in VtdDxe.
This information is to record which device requested which DMA buffer.
It can be used for DMA buffer analysis.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-03-09 10:27:52 +08:00
Star Zeng 339cb0af96 IntelSiliconPkg VTdPmrPei: Add PcdVTdPeiDmaBufferSize(S3)
Add PcdVTdPeiDmaBufferSize(S3) to replace the hard coded value
TOTAL_DMA_BUFFER_SIZE and TOTAL_DMA_BUFFER_SIZE_S3 in IntelVTdPmrPei.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-03-06 22:31:49 +08:00
Star Zeng abe63fa7dc IntelSiliconPkg VTdPmrPei: Return SUCCESS when Mapping == NULL in Unmap
NULL is returned to Mapping when Operation is BusMasterCommonBuffer or
BusMasterCommonBuffer64 in PeiIoMmuMap().
So Mapping == NULL is valid when calling PeiIoMmuUnmap().

940dbd071e wrongly changed EFI_SUCCESS
to EFI_INVALID_PARAMETER when Mapping == NULL in PeiIoMmuUnmap().
This patch is to correct it.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-03-06 22:31:48 +08:00
Star Zeng 940dbd071e IntelSiliconPkg IntelVTdPmrPei: Install IOMMU PPI for pre-memory phase
Install IOMMU PPI for pre-memory phase and return
EFI_NOT_AVAILABLE_YET to indicate that DMA protection has been enabled,
but DMA buffer are not available to be allocated yet.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-02-07 18:28:12 +08:00
Star Zeng ed0e52fc9a IntelSiliconPkg IntelVTdPmrPei: Install IoMmu PPI before enabling PMR
Then the consumer of IoMmu PPI has opportunity to get granted DMA
buffer (by callback) to replace old buffer before it is forbidden
by enabling PMR.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-02-07 18:28:11 +08:00
Star Zeng 17ac6b23dc IntelSiliconPkg PlatformVTdSampleDxe: State it is only for dev/debug
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-02-07 09:22:02 +08:00
Hao Wu 2ad34f65af IntelSiliconPkg/MicrocodeUpdateDxe: Refine debug messages
Refine the debug messages during the verification of microcode to make
them more clear.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-02-02 11:36:10 +08:00
Star Zeng 1db271df76 IntelSiliconPkg MicrocodeUpdateDxe: TotalSize must be multiples of 1KB
TotalSize must be multiples of 1024 bytes (1 KBytes) according to SDM.

Also enhance the debug message for DataSize that must be
multiples of DWORDs.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-26 18:21:04 +08:00
Star Zeng bac7f02365 IntelSiliconPkg IntelVTdDxe: Fix flush cache issue
The patch fixes flush cache issue in
CreateSecondLevelPagingEntryTable().

We found some video cards still not work even they have
been added to the exception list.

In CreateSecondLevelPagingEntryTable(), the check
"(BaseAddress >= MemoryLimit)" may be TRUE and "goto Done"
will be executed, then the FlushPageTableMemory operations
at the end of the function will be skipped.

Instead of "goto Done", this patch uses "break" to break
the for loops, then the FlushPageTableMemory operations
at the end of the function could have opportunity to be
executed.

The patch also fixes a miscalculation for Lvl3End.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-24 18:40:36 +08:00
Star Zeng 1d4c17a6ef IntelSiliconPkg IntelVTdDxe: Fix DMA does not work issue
Fix DMA does not work issue when system memory is not
greater than 4G.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-18 10:36:56 +08:00
Star Zeng b2725f57c7 IntelSiliconPkg IntelVTdPmrPei: Get high top by host address width
Get high top by host address width instead of resource HOB.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-17 18:34:46 +08:00
Star Zeng 9eaa902a52 IntelSiliconPkg IntelVTdDxe: Remove mVtdHostAddressWidthMask
mVtdHostAddressWidthMask is not been used at all,
its definition and related code could be removed.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-17 10:49:02 +08:00
Star Zeng 9dd8b1908e IntelSiliconPkg IntelVTdPmrPei: Use HostAddressWidth in DMAR correctly
According to VTd spec, HostAddressWidth + 1 should be used as the real
host address width value.

Host Address Width:
This field indicates the maximum DMA physical
addressability supported by this platform. The
system address map reported by the BIOS
indicates what portions of this addresses are
populated.
The Host Address Width (HAW) of the platform is
computed as (N+1), where N is the value
reported in this field. For example, for a platform
supporting 40 bits of physical addressability, the
value of 100111b is reported in this field.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-17 10:48:57 +08:00
Star Zeng e8097a74b7 IntelSiliconPkg IntelVTdPmrPei: Refine comments about PHMR/PLMR.Limit
According to VTd spec, the real hardware decoded limit should be
PHMR/PLMR.Limit value + alignment value.

"Bits N:0 of the limit register are
decoded by hardware as all 1s."

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-17 10:34:22 +08:00
Star Zeng 01bd1c98fa IntelSiliconPkg IntelVTdDxe: Fix potential NULL pointer dereference
The implementation of MdeModulePkg\Universal\Acpi\AcpiTableDxe reserves
first entry of RSDT/XSDT to FADT, the first entry value is 0 when FADT
is not installed. So the RSDT/XSDT parsing code should check the entry
value first before checking the table signature.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-16 09:01:50 +08:00
Star Zeng 0bc94c748b IntelSiliconPkg IntelVTdDxe: Support early SetAttributes()
Support early SetAttributes() before DMAR table is installed.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-05 10:26:34 +08:00
Star Zeng 3a71670618 IntelSiliconPkg IntelVTdDxe: Use TPL to protect list/engine operation
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-05 10:26:33 +08:00
Star Zeng dcd39e09ff IntelSiliconPkg IntelVTdDxe: Signal AcpiNotificationFunc() initially
Signal AcpiNotificationFunc() initially for the case that
DMAR table has been installed when creating event.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-05 10:26:32 +08:00
Star Zeng 3bd91ae236 IntelSiliconPkg MicrocodeUpdateDxe: Fix (ExtendedTableLength & 0x3)!=0
The first 48 bytes contain the microcode update header.
DataSize must be a multiple of DWORDs.
TotalSize is always a multiple of 1024.
Both size of CPU_MICROCODE_EXTENDED_TABLE_HEADER and
CPU_MICROCODE_EXTENDED_TABLE are multiple of DWORDs.

So (ExtendedTableLength & 0x3)!=0 should be
(ExtendedTableLength & 0x3)==0.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
2017-12-21 18:34:55 +08:00
Star Zeng 34e18d1758 IntelSilicon: Correct function description for AllocateBuffer
DUAL_ADDRESS_CYCLE is missing in the EFI_UNSUPPORTED
return status description.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2017-12-12 09:31:55 +08:00
Star Zeng 0a9e1f6841 IntelSiliconPkg: Update MicrocodeUpdate build path in dsc
That was missed in 43e12eeac8.

Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-12-01 09:31:52 +08:00
Star Zeng 43e12eeac8 IntelSiliconPkg: Update MicrocodeUpdate to build with the package
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540

This is after patch
"IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkg".

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2017-11-30 09:25:28 +08:00
Star Zeng c8a2f3c332 IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkg
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540

To consume FIT table for Microcode update,
UefiCpuPkg/Feature/Capsule/MicrocodeUpdateDxe
needs to be updated to consume
IntelSiliconPkg/Include/IndustryStandard/FirmwareInterfaceTable.h,
but UefiCpuPkg could not depend on IntelSiliconPkg.

Since the Microcode update feature is specific to Intel,
we can first move the Microcode update feature code from
UefiCpuPkg to IntelSiliconPkg [first step], then update
the code to consume FIT table [second step].

This patch series is for the first step.

Note: No any code change in this patch, just move.
Next patch will update MicrocodeUpdate to build with the package.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2017-11-30 09:25:28 +08:00
Star Zeng 7729e3c448 IntelSiliconPkg IntelVTdDxe: Do not SetupVtd again
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Tested-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-11-23 10:43:43 +08:00
Star Zeng f6f486e7bf IntelSiliconPkg IntelVTdDxe: Use ACPI table event to get DMAR table
Use ACPI table event to get DMAR table instead of using ACPI SDT
notification as ACPI SDT is optional and the default value of
PcdInstallAcpiSdtProtocol is FALSE in MdeModulePkg.dec.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-11-06 10:08:48 +08:00
Jiewen Yao af807bb986 IntelSiliconPkg/VtdPeiSample: Add premem support.
Before memory is ready, this sample produces one VTd engine.
After memory and silicon is initialized, this sample produces
both IGD VTd engine and all-rest VTd engine by reinstall the
FV_INFO_PPI.

This update is to demonstrate how to support pre-mem VTd usage.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-10-30 09:27:56 +08:00
Jiewen Yao a1e7cd0b02 IntelSiliconPkg/VtdPmrPei: Add premem support.
Remove memory discovered dependency to support both premem
VTD_INFO_PPI and postmem VTD_INFO_PPI.

If VTD_INFO_PPI is installed before memory is ready, this
driver protects all memory region.
If VTD_INFO_PPI is installed or reinstalled after memory
is ready, this driver allocates DMA buffer and protect rest.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-10-30 09:27:55 +08:00
Jiewen Yao e5d847476a IntelSiliconPkg/VTdDxe: return unsupported for exceptionlist
Since the exception list is not a recommended way, we returns
EFI_UNSUPPORTED in the sample code.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-10-30 09:25:54 +08:00
Jiewen Yao 01df510319 IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.
Change ExitBootServices TPL to CALLBACK, so that a device
can disable BME before IOMMU grants access right.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-10-30 09:25:52 +08:00
Star Zeng 118f1657b9 IntelSiliconPkg IntelVTdDxe: use gEfiAcpi10TableGuid for ACPI 1.0
According to definition (Acpi.h and MdePkg.dec),
gEfiAcpiTableGuid = gEfiAcpi20TableGuid, and the code is trying
to parse ACPI 2.0 first and then ACPI 1.0, but it uses
gEfiAcpiTableGuid wrongly for ACPI 1.0, this patch is to fix it.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-10-26 17:58:44 +08:00
Jiewen Yao c13cb4aebf IntelSiliconPkg/VtdInfoSample: Fix IGD RMRR memory.
Fix a calculation problem in IGD RMRR memory.

Cc: Zeng Star <zeng.star@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Zeng Star <zeng.star@intel.com>
2017-10-24 10:45:54 +08:00
Jiewen Yao fc8be1ad9a IntelSiliconPkg/VTdPmrPei: Add EndOfPei callback for S3
In S3 resume, before system transfer to waking vector,
the VTdPmr need turn off VTd protection based upon VTdPolicy.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-23 16:14:30 +08:00
Jiewen Yao 8be3ff8fb8 IntelSiliconPkg/dec: Clarify VTdPolicy.
Clarify the VTdPolicy is for both PEI and DXE.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-23 16:14:28 +08:00
Jiewen Yao 73a2fe8b87 IntelSiliconPkg/VTdDxe: Clean up DXE flush memory.
Make sure the context table are flush to memory.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-23 16:14:27 +08:00
Jiewen Yao 70dc3ec5a7 IntelSiliconPkg/VTdInfoSample: Add RMRR table.
Let system report RMRR table for the platform support
PEI graphic.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-20 14:45:45 +08:00
Jiewen Yao 8e9da4ba3c IntelSiliconPkg/IntelVTdPmrPei: Parse RMRR table.
In order to support PEI graphic, we let VTdPmrPei driver
parse DMAR table RMRR entry and allow the UMA access.

If a system has no PEI IGD, no RMRR is needed. The behavior
is unchanged.

If a system has PEI IGD, it must report RMRR in PEI phase.
The PeiVTdPrm will program the IGD VTd engine to skip the
RMRR region, and program the rest PCI VTd engine to skip
the another DMA buffer allocated in PEI phase for other
device driver.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-20 14:45:43 +08:00
Jiewen Yao f02c531967 IntelSiliconPkg/VTdInfoPpi: Let it follow DMAR table.
We notice that there is real usage in PEI to show
the graphic out. As such we need report RMRR table
in PEI to let VTdPmrPei driver skip the IGD UMA region.

Now the VTD_INFO PPI uses the same DMAR data structure.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-20 14:45:42 +08:00