Commit Graph

13 Commits

Author SHA1 Message Date
Star Zeng 9e9ca2100f UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte aligned
As HOB which has 8byte aligned requirement will be built based on them
in PEI phase.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2017-08-01 17:49:14 +08:00
Dandan Bi 367284e773 UefiCpuPkg: Make the comments align with the functions
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-14 21:34:42 +08:00
Jeff Fan ec16deeac9 UefiCpuPkg/SecCore: Correct print format for stack information
v2:
  Per Laszlo and Andrew's comments at
    https://lists.01.org/pipermail/edk2-devel/2016-November/004759.html
  SecCoreData->StackBase is VOID * type. We should use %p to dump VOID * type.
  SecCoreData->StackSize is UINTN type, but %x only could print unsinged-int
  type. We will cast it to UINT32 firstly and then use %x to print it.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-11-18 09:43:53 +08:00
Jeff Fan af34c10649 UefiCpuPkg: Display new stack base and size
Dump new stack base and size information could help developer to narrow down
stack crash issue.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-09 16:00:15 +08:00
Jeff Fan 93638568c1 UefiCpuPkg/SecCore: SecPlatformInformation(2) are optional PPIs
Currently, this is ASSERT() if neither SecPlatformInformation2 nor
SecPlatformInformation PPIs are found. This is not correct. Per PI specification
both of them are optional PPI. Platform may not install them.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-21 14:12:49 +08:00
Jeff Fan 030d2de7c7 UefiCpuPkg/SecCore: Fix comment typo
Revert SecPlatformInformation2 and SecPlatformInformation in two comment blocks.
And correct the words.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-21 14:12:45 +08:00
Jeff Fan 8a5b8cef67 UefiCpuPkg/SecCore: Re-install SEC platform information(2) PPI
In SecTemporaryRamDone(), we will build one privated GUIDed-HOB to save CPU BIST
Data and re-install SEC platform information(2) PPI. Then other PEI drivers
could get CPU BIST data from the private GUIDed-HOB by new installed PPI.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14 08:54:46 +08:00
Jeff Fan d157de8b56 UefiCpuPkg/SecCore: Abstract worker function GetBistFromHob()
Abstract one worker function to get CPU BIST from the GUIDed-HOB. Add
SecPlatformInformationBist() and SecPlatformInformation2Bist() to invoke
GetBistFromHob(). Add in/out for parameter in function header.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14 08:54:42 +08:00
Jeff Fan 863c738c4a UefiCpuPkg/SecCore: Add SecBist.c
Add SecBist.c and copy GetBistInfoFromPpi() and SecPlatformInformation2() from
UefiCpuPkg/CpuMpPei/CpuBist.c. And update SecMain.c, SecMain.inf and
UefiCpuPkg.dsc accordinlgy to pass build.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14 08:54:39 +08:00
Liming Gao 9caff8d961 UefiCpuPkg SecCore: Update SecCore inf to refer to nasmb source
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-11 13:20:21 +08:00
Marvin H?user 61257251b2 UefiCpuPkg/SecMain: Decorate phase-transition function with NORETURN.
This patch adds the NORETURN attribute to the function that transfers
to the PEI phase, along with an UNREACHABLE() call at the end to
avoid false warnings.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-06-22 09:37:22 +08:00
Jordan Justen 5999b89e22 UefiCpuPkg: Convert all .uni files to utf-8
To convert these files I ran:

$ python3 BaseTools/Scripts/ConvertUni.py UefiCpuPkg

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19264 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15 04:59:14 +00:00
Michael Kinney 1921695e64 UefiCpuPkg: Add SecCore module
Add SecCore module that uses the PlatformSecLib class for platform
specific actions.  The SecCore module also uses a new PCD to
configure the size of the stack used in the SEC phase.  If the
stack size PCD is set to 0, the stack is configured to use half
of the available temporary RAM.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18636 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-19 19:10:14 +00:00