Commit Graph

4 Commits

Author SHA1 Message Date
Star Zeng b2725f57c7 IntelSiliconPkg IntelVTdPmrPei: Get high top by host address width
Get high top by host address width instead of resource HOB.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-17 18:34:46 +08:00
Jiewen Yao a1e7cd0b02 IntelSiliconPkg/VtdPmrPei: Add premem support.
Remove memory discovered dependency to support both premem
VTD_INFO_PPI and postmem VTD_INFO_PPI.

If VTD_INFO_PPI is installed before memory is ready, this
driver protects all memory region.
If VTD_INFO_PPI is installed or reinstalled after memory
is ready, this driver allocates DMA buffer and protect rest.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-10-30 09:27:55 +08:00
Jiewen Yao 8e9da4ba3c IntelSiliconPkg/IntelVTdPmrPei: Parse RMRR table.
In order to support PEI graphic, we let VTdPmrPei driver
parse DMAR table RMRR entry and allow the UMA access.

If a system has no PEI IGD, no RMRR is needed. The behavior
is unchanged.

If a system has PEI IGD, it must report RMRR in PEI phase.
The PeiVTdPrm will program the IGD VTd engine to skip the
RMRR region, and program the rest PCI VTd engine to skip
the another DMA buffer allocated in PEI phase for other
device driver.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-20 14:45:43 +08:00
Jiewen Yao db5c75863d IntelSiliconPkg/IntelVTdPmrPei: Move to feature dir.
Move IntelVTdPmrPei to Feature/VTd/IntelVTdPmrPei.

Suggested-by: Star Zeng <star.zeng@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-17 09:52:13 +08:00