Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
Current CorebootPayloadPkgIa32X64.dsc contains "-flto" flag to
request GCC link time optimization. However, this feature is
only supported by newer GCC compiler, and it will break the
debug build with GCC4.8. To fix it, the extra compiling flags
are removed. It allows the default build flags set by the EDKII
build environment to be used.
With this fix, CorebootPayloadPkg 64bit debug build can pass
using GCC 4.8.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
On old platform without PCIe express support, the PciLib needs to
be mapped to PciLibCf8 instance to make it work. On new platform
with PCIe express support, the PciLib needs to be mapped to
PciLibPciExpress to allow access to extended PCIe configuration
space. This patch allows to select the PciLib instance between
PciLibCf8 and PciLibPciExpress using the PCIE_BASE macro through
build command line.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
The previous change to disable deprecated APIs in CorebootPayloadPkg
used "/D" instead of "-D". It caused Linux GCC build error. Correct
it to use "-D" instead.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Rusty Coleman <rcoleman@sigovs.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Rusty Coleman <rcoleman@sigovs.com>
The current CorebootPayloadPkg will use the legacy 8254 timer
driver as the default. However, on some platforms legacy timer
might not exist anymore. This patch adds HPET timer driver as
a build option.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by : Prince Agyeman <prince.agyeman@intel.com>
Update CbSupportPei to consume the new library, so platform could provide
platform specific library instance to parse platform specif info.
And add a NULL library instance to pass build.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: gdong1 <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Add the following definition in the [BuildOptions] section in package DSC
files to disable APIs that are deprecated. As a result replaced PcdSet32
with PcdSet32S accordingly to make the build pass.
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
Cc: Prince Agyeman <prince.agyeman@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=163
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
The current CorebootPayloadPkg will print the following message
"InsertImageRecord - Section Alignment(0x20) is not 4K" during
boot. It is caused by the section alignment arranged by the linker.
This patch change the alignment to 4K for runtime drivers.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
The current CorebootPayloadPkg uses PEI/DXE StatusCode drivers from
IntelFrameworkModulePkg. This patch switches to use the StatusCode
driver from MdeModulePkg instead.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
MpInitLib is consumed by CpuDxe
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
Reviewed by: Maurice Ma <maurice.ma@intel.com>
Current CorebootPayloadPkg uses PciBusNoEnumerationDxe and
PciRootBridgenoEnumerationDxe copied from the DuetPkg. Now it will
switch to use the standard PciBusDxe and PciHostBridgeDxe from
MdeModulePkg. As a result, a coreboot specific PciHostBridgeLib
is added to collect pre-allocated PCI resources.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Switch over to use BdxDxe generic driver in MdeModulePkg.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Use generic SerialDxe driver in MdeModulePkg instead of the one
in CorebootModulePkg. By doing this the reference for
PciSioSerialDxe driver will also be removed from DSC and FDF file.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Add the USB OHCI driver from revision 24ca2f35 of QuarkSocPkg.
Change-Id: Ie7aa0bc47d4ff06adc57976a5efb0e40ce4e1673
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Add SD and eMMC DXE driver support to CorebootPayloadPkg.
Change-Id: Ibfd3a2cc32a653ce51e38d9157ea3c6da25a5474
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Set the proper Shell file GUID so that the BDS transfers control to the
Shell.
Change-Id: I816636a340bbe2f76ac1973b9cb685084c4f88a0
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Use the BaseSerialPortLib16550 which sets RTS and DTR during
initialization. This fixes the mis-matched flow control issue when
the flow control signals are connected between the host and target
and the host has flow control enabled.
Change-Id: I3505e129b2de3c5c17fff23c62553f15cd892dca
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Set the vendor to 0xffff which indicates the end of the list.
Change-Id: If6475e04d3675f0a932571a85d1dd3f301416b6a
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
eviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Convert to using DOS line endings.
Change-Id: Ie2f148867d9b2b386d556583afb6716ec21399e9
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Use the serial drivers which update the serial PCDs from
PlatformHookLib.
Change-Id: Ie6a3526d56332ee1cf07edb24ff39634a981183f
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Add a define and use it with MaxLogicalProcessorNumber to enable this
PCD to be changed via the command line. Quark needs to set this value
to one during the builds.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Allow the serial port configuration to be overriden from the command
line.
Make the debug serial PCDs patchable in module.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Add all of the shell options from ShellBinPkg including building the
shell from source.
Enable link time optimization for GCC debug builds to keep the size
under 0x3e0000.
Test: Use -DSHELL_TYPE=BUILD_SHELL command line options to build the
shell from source. Run the result on Galileo Gen2.
Change-Id: I1e12adb57960ac5e75e682073540a9322aa03081
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Remove the references to DuetPkg. Copy the files from revision
ffea0a2ce2 of DuetPkg into
CorebootModulePkg. The components include:
* PciBusNoEnumerationDxe
* PciRootBridgeNoEnumerationDxe
* SataControllerDxe
TEST=Build and run on Galileo Gen2
Change-Id: Id07185f7e226749e5f7c6b6cb427bcef7eac8496
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Remove trailing white space from existing .dsc and .fdf files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Now that FatPkg is open source (and therefore can be included in the
EDK II tree) we build and use it directly.
Note: Build tested with GCC 5.3 on IA32 and IA32+X64.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
1. Update fdf and dsc to use SerialDxe in MdeModulePkg.
2. Separate the code that gets SerialRegBase and SerialRegAccessType
by CbParseLib from CorebootPayloadPkg/Library/SerialPortLib to
PlatformHookLib, and then leverage BaseSerialPortLib16550 in
MdeModulePkg.
3. Remove CorebootPayloadPkg/SerialDxe and
CorebootPayloadPkg/Library/SerialPortLib.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18968 6f19259b-4bc3-4df7-8a09-765794883524
Current CorebootPayloadPkg uses PciHostBridge and PciBusNoEnumeration
driver. It will cause the PCI bus resource incorrectly set in root
bridge instance. As a result all PCI devices behind a PCI bridge will
not show up in Shell 'PCI' command.
To resolve it use PciRootBridgeNoEnumeration driver instead.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17408 6f19259b-4bc3-4df7-8a09-765794883524
Ruiyu Ni
Maurice Ma
gdong1
Prince Agyeman
Leahy, Leroy P
Justen, Jordan L
Star Zeng
Jordan Justen