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9 Commits

Author SHA1 Message Date
Jiewen Yao fc8be1ad9a IntelSiliconPkg/VTdPmrPei: Add EndOfPei callback for S3 
In S3 resume, before system transfer to waking vector,
the VTdPmr need turn off VTd protection based upon VTdPolicy.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
 2017-09-23 16:14:30 +08:00
Jiewen Yao 73a2fe8b87 IntelSiliconPkg/VTdDxe: Clean up DXE flush memory. 
Make sure the context table are flush to memory.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
 2017-09-23 16:14:27 +08:00
Jiewen Yao 70dc3ec5a7 IntelSiliconPkg/VTdInfoSample: Add RMRR table. 
Let system report RMRR table for the platform support
PEI graphic.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
 2017-09-20 14:45:45 +08:00
Jiewen Yao 8e9da4ba3c IntelSiliconPkg/IntelVTdPmrPei: Parse RMRR table. 
In order to support PEI graphic, we let VTdPmrPei driver
parse DMAR table RMRR entry and allow the UMA access.

If a system has no PEI IGD, no RMRR is needed. The behavior
is unchanged.

If a system has PEI IGD, it must report RMRR in PEI phase.
The PeiVTdPrm will program the IGD VTd engine to skip the
RMRR region, and program the rest PCI VTd engine to skip
the another DMA buffer allocated in PEI phase for other
device driver.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
 2017-09-20 14:45:43 +08:00
Jiewen Yao 4084ccfa22 IntelSiliconPkg/VTdPei: Fix Linux build error. 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
 2017-09-18 08:56:39 +08:00
Jiewen Yao bec7a86c70 IntelSiliconPkg/PlatformIntelVTdInfoSamplePei: Move to feature dir. 
Move PlatformIntelVTdInfoSamplePei to Feature/VTd/.

Suggested-by: Star Zeng <star.zeng@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
 2017-09-17 09:52:15 +08:00
Jiewen Yao db5c75863d IntelSiliconPkg/IntelVTdPmrPei: Move to feature dir. 
Move IntelVTdPmrPei to Feature/VTd/IntelVTdPmrPei.

Suggested-by: Star Zeng <star.zeng@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
 2017-09-17 09:52:13 +08:00
Jiewen Yao e4c9ac648d IntelSiliconPkg/PlatformVTdSampleDxe: Move to feature dir. 
Move PlatformVTdSampleDxe to Feature/VTd/PlatformVTdSampleDxe.

Suggested-by: Star Zeng <star.zeng@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
 2017-09-17 09:52:12 +08:00
Jiewen Yao 9010459c9a IntelSiliconPkg/IntelVTdDxe: Move to feature dir. 
Move IntelVTdDxe to Feature/VTd/IntelVTdDxe.

Suggested-by: Star Zeng <star.zeng@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
 2017-09-17 09:52:10 +08:00