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2 Commits

Author SHA1 Message Date
Tuan Phan 772ec92577 UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode 
Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATP mode
during bring up to debug memory map issue.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
 2023-10-17 07:44:25 +00:00
Tuan Phan f220dcbba8 UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode 
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
 2023-07-15 14:10:18 +00:00