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2d2642f483
When re-entering EDK2 from a high level OS such as Linux, the GICv3 may be configured to use split priority drop and deactivate (EOImode == 1), whereas EDK2's GICv3 driver assumes the default setting of EOImode == 0. So clear the EOImode bit explicitly when taking control of the GIC. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
127 lines
5.5 KiB
C
127 lines
5.5 KiB
C
/** @file
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*
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* Copyright (c) 2011-2023, Arm Limited. All rights reserved.<BR>
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef ARMGIC_H_
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#define ARMGIC_H_
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// GIC Distributor
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#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
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#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
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#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
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// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
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#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
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#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
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#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
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#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
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#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
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#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
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// Each reg base below repeats for Number of interrupts / 4
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#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
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// Each reg base below repeats for Number of interrupts
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#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
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#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
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#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
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// just one of these
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#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
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// GICv3 specific registers
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#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
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// GICD_CTLR bits
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#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
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#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
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// GICD_ICDICFR bits
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#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register
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#define ARM_GIC_ICDICFR_BYTES (ARM_GIC_ICDICFR_WIDTH / 8)
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#define ARM_GIC_ICDICFR_F_WIDTH 2 // Each F field is 2 bits
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#define ARM_GIC_ICDICFR_F_STRIDE 16 // (32/2) F fields per register
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#define ARM_GIC_ICDICFR_F_CONFIG1_BIT 1 // Bit number within F field
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#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt
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#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt
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// GIC Redistributor
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#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
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#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
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#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
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#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
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// GIC Redistributor Control frame
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#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
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// GIC Redistributor TYPER bit assignments
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#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
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#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
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#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
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#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
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#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
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// Selection Support
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#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
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#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
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#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
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#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \
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ARM_GICR_TYPER_AFFINITY) >> 32)
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// GIC SGI & PPI Redistributor frame
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#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
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#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
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// GIC Cpu interface
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#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
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#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
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#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
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#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
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#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
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#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
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#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
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#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
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#define ARM_GIC_ICCIIDR 0xFC // Identification Register
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#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
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#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
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#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
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// Bit-masks to configure the CPU Interface Control register
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#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
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#define ARM_GIC_ICCICR_ENABLE_NS 0x02
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#define ARM_GIC_ICCICR_ACK_CTL 0x04
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#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
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#define ARM_GIC_ICCICR_USE_SBPR 0x10
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// Bit Mask for GICC_IIDR
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#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
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#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
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#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
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#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
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// Bit Mask for
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#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
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//
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// GIC SPI and extended SPI ranges
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//
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#define ARM_GIC_ARCH_SPI_MIN 32
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#define ARM_GIC_ARCH_SPI_MAX 1019
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#define ARM_GIC_ARCH_EXT_SPI_MIN 4096
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#define ARM_GIC_ARCH_EXT_SPI_MAX 5119
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// GIC revision 3 specific declarations
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#define ICC_SRE_EL2_SRE (1 << 0)
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#define ICC_CTLR_EOImode (1 << 1)
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#define ARM_GICD_IROUTER_IRM BIT31
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#endif // ARMGIC_H_
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