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1715d67231
A ArmReadIdAA64Isar0Reg() function was recently added to BaseLib. Use it instead of its ArmReadIdIsar0() equivalent, which was private to the BaseRngLib library. This also allows to avoid the confusion between the following registers: - ID_ISAR0_EL1: allows to probe for Divide instructions, Debug instructions, ... - ID_AA64ISAR0_EL1: AARCH64 specific register allowing to probe for AESE, RNDR, ... instructions Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
68 lines
1.6 KiB
INI
68 lines
1.6 KiB
INI
## @file
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# Instance of RNG (Random Number Generator) Library.
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#
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# BaseRng Library that uses CPU RNG instructions (e.g. RdRand) to
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# provide random numbers.
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#
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# Copyright (c) 2023, Arm Limited. All rights reserved.<BR>
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# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
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# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = BaseRngLib
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MODULE_UNI_FILE = BaseRngLib.uni
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FILE_GUID = 626440D8-1971-41D9-9AB2-FB25F4AE79BC
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = RngLib
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CONSTRUCTOR = BaseRngLibConstructor
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#
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# VALID_ARCHITECTURES = IA32 X64 AARCH64
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#
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[Sources]
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BaseRng.c
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BaseRngLibInternals.h
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[Sources.Ia32, Sources.X64]
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Rand/RdRand.c
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[Sources.AARCH64]
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AArch64/Rndr.c
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AArch64/ArmRng.h
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AArch64/ArmRng.S | GCC
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AArch64/ArmRng.asm | MSFT
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[Guids.AARCH64]
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gEfiRngAlgorithmArmRndr
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[Guids.Ia32, Guids.X64]
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gEfiRngAlgorithmSp80090Ctr256Guid
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[Sources.RISCV64]
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Riscv/Rng.c
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Riscv/Seed.S | GCC
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[Packages]
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MdePkg/MdePkg.dec
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[Pcd.AARCH64]
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gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm
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[LibraryClasses]
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BaseLib
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DebugLib
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[Pcd.RISCV64]
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# Does the CPU support the Zkr extension (for the `Seed` CSR)
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gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES
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