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2eff4ddc77
To substantially reduce the amount of processing that takes place with the MMU and caches off, implement a version of ArmPlatformLib specific for QEMU/mach-virt in AArch64 mode that carries a statically allocated and populated ID map that covers the NOR flash and device region, and 128 MiB of DRAM at the base of memory (0x4000_0000). Note that 128 MiB has always been the minimum amount of DRAM we support for this configuration, and the existing code already ASSERT()s in DEBUG mode when booting with less. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
116 lines
3.5 KiB
ArmAsm
116 lines
3.5 KiB
ArmAsm
//
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// Copyright (c) 2022, Google LLC. All rights reserved.
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//
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#include <AsmMacroIoLibV8.h>
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.macro mov_i, reg:req, imm:req
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movz \reg, :abs_g3:\imm
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movk \reg, :abs_g2_nc:\imm
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movk \reg, :abs_g1_nc:\imm
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movk \reg, :abs_g0_nc:\imm
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.endm
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.set MAIR_DEV_nGnRnE, 0x00
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.set MAIR_MEM_NC, 0x44
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.set MAIR_MEM_WT, 0xbb
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.set MAIR_MEM_WBWA, 0xff
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.set mairval, MAIR_DEV_nGnRnE | (MAIR_MEM_NC << 8) | (MAIR_MEM_WT << 16) | (MAIR_MEM_WBWA << 24)
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.set TCR_TG0_4KB, 0x0 << 14
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.set TCR_TG1_4KB, 0x2 << 30
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.set TCR_IPS_SHIFT, 32
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.set TCR_EPD1, 0x1 << 23
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.set TCR_SH_INNER, 0x3 << 12
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.set TCR_RGN_OWB, 0x1 << 10
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.set TCR_RGN_IWB, 0x1 << 8
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.set tcrval, TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1 | TCR_RGN_OWB
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.set tcrval, tcrval | TCR_RGN_IWB | TCR_SH_INNER
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.set SCTLR_ELx_I, 0x1 << 12
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.set SCTLR_ELx_SA, 0x1 << 3
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.set SCTLR_ELx_C, 0x1 << 2
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.set SCTLR_ELx_M, 0x1 << 0
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.set SCTLR_EL1_SPAN, 0x1 << 23
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.set SCTLR_EL1_WXN, 0x1 << 19
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.set SCTLR_EL1_SED, 0x1 << 8
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.set SCTLR_EL1_ITD, 0x1 << 7
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.set SCTLR_EL1_RES1, (0x1 << 11) | (0x1 << 20) | (0x1 << 22) | (0x1 << 28) | (0x1 << 29)
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.set sctlrval, SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_ITD | SCTLR_EL1_SED
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.set sctlrval, sctlrval | SCTLR_ELx_I | SCTLR_EL1_SPAN | SCTLR_EL1_RES1
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ASM_FUNC(ArmPlatformPeiBootAction)
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mrs x0, CurrentEL // check current exception level
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tbz x0, #3, 0f // bail if above EL1
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ret
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0:mov_i x0, mairval
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mov_i x1, tcrval
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adrp x2, idmap
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orr x2, x2, #0xff << 48 // set non-zero ASID
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mov_i x3, sctlrval
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mrs x6, id_aa64mmfr0_el1 // get the supported PA range
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and x6, x6, #0xf // isolate PArange bits
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cmp x6, #6 // 0b0110 == 52 bits
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sub x6, x6, #1 // subtract 1
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cinc x6, x6, ne // add back 1 unless PArange == 52 bits
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bfi x1, x6, #32, #3 // copy updated PArange into TCR_EL1.IPS
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cmp x6, #3 // 0b0011 == 42 bits
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sub x6, x6, #1 // subtract 1
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cinc x6, x6, lt // add back 1 unless VA range >= 42
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mov x7, #32
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sub x6, x7, x6, lsl #2 // T0SZ for PArange != 42
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mov x7, #64 - 42 // T0SZ for PArange == 42
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csel x6, x6, x7, ne
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orr x1, x1, x6 // set T0SZ field in TCR
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cmp x6, #64 - 40 // VA size < 40 bits?
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add x4, x2, #0x1000 // advance to level 1 descriptor
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csel x2, x4, x2, gt
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msr mair_el1, x0 // set up the 1:1 mapping
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msr tcr_el1, x1
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msr ttbr0_el1, x2
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isb
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tlbi vmalle1 // invalidate any cached translations
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ic iallu // invalidate the I-cache
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dsb nsh
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isb
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msr sctlr_el1, x3 // enable MMU and caches
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isb
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ret
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//UINTN
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//ArmPlatformGetCorePosition (
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// IN UINTN MpId
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// );
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// With this function: CorePos = (ClusterId * 4) + CoreId
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ASM_FUNC(ArmPlatformGetCorePosition)
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mov x0, xzr
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ret
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//UINTN
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//ArmPlatformGetPrimaryCoreMpId (
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// VOID
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// );
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ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
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MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
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ret
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//UINTN
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//ArmPlatformIsPrimaryCore (
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// IN UINTN MpId
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// );
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ASM_FUNC(ArmPlatformIsPrimaryCore)
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mov x0, #1
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ret
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