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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4114 1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer respectively in TempRamInitApi in IA32 FspSecCoreT. 2.Correct inappropriate description in the return value of AsmGetFspInfoHeader. 3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in FspHeler.nasm. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
37 lines
1.0 KiB
NASM
37 lines
1.0 KiB
NASM
;; @file
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; Provide FSP helper function.
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;
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; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;;
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DEFAULT REL
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SECTION .text
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FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
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global ASM_PFX(AsmGetFspBaseAddress)
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ASM_PFX(AsmGetFspBaseAddress):
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call ASM_PFX(AsmGetFspInfoHeader)
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add rax, FSP_HEADER_IMGBASE_OFFSET
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mov eax, [rax]
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ret
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global ASM_PFX(AsmGetFspInfoHeader)
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ASM_PFX(AsmGetFspInfoHeader):
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lea rax, [ASM_PFX(AsmGetFspInfoHeader)]
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DB 0x48, 0x2d ; sub rax, 0x????????
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global ASM_PFX(FspInfoHeaderRelativeOff)
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ASM_PFX(FspInfoHeaderRelativeOff):
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DD 0x12345678 ; This value must be patched by the build script
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and rax, 0xffffffff
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ret
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global ASM_PFX(AsmGetFspInfoHeaderNoStack)
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ASM_PFX(AsmGetFspInfoHeaderNoStack):
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lea rax, [ASM_PFX(AsmGetFspInfoHeader)]
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lea rcx, [ASM_PFX(FspInfoHeaderRelativeOff)]
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mov ecx, [rcx]
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sub rax, rcx
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and rax, 0xffffffff
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jmp rdi
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