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When allocating memory to perform non-coherent DMA, use the cache writeback granule rather than the data cache linesize for alignment. This prevents the explicit cache maintenance from corrupting unrelated adjacent data if the cache writeback granule exceeds the cache linesize. Reported-by: Mark Rutland <mark.rutland@arm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18759 6f19259b-4bc3-4df7-8a09-765794883524