mirror of https://github.com/acidanthera/audk.git
a05a8a5aa1
Put the UART in FIFO Polled Mode by clearing IER after setting FCR. Also, add comments to show DLAB state for registers 0 and 1. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran <leo.duran@amd.com> Cc: Star Zeng <star.zeng@intel.com> CC: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> |
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Application | ||
Bus | ||
Core | ||
Include | ||
Library | ||
Logo | ||
Universal | ||
MdeModulePkg.dec | ||
MdeModulePkg.dsc | ||
MdeModulePkg.uni | ||
MdeModulePkgExtra.uni |