mirror of https://github.com/acidanthera/audk.git
6052a15f4a
According to AHCI Spec 1.3 GHC.AE bit description: "The implementation of this bit is dependent upon the value of the CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be read-only and shall have a reset value of '1'." Being in AhciMode, for proper operation it is required, that GHC.AE bit is always set, before any other AHCI registers are written to. Current AhciMode implementation, both in AhciReset() and AhciModeInitialization() functions, set GHC.AE bit only depending on 'CAP.SAM == 0' condition, assuming (according to the AHCI spec), that otherwise it has to be set anyway. It may however happen, that even if 'CAP.SAM == 1', GHC.AE requires updating by software. This patch enables in AhciMode setting GHC.AE in case its initial value is '0'. It fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC families. The change is transparent to all other platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Jan Dabros <jsd@semihalf.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> |
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| .. | ||
| Ata | ||
| I2c/I2cDxe | ||
| Isa | ||
| Pci | ||
| Scsi | ||
| Sd | ||
| Ufs | ||
| Usb | ||