mirror of https://github.com/acidanthera/audk.git
c248802e40
On modern platforms with TBT devices the coreboot resource allocator opens large PCI bridge MMIO windows above 4GiB to place hotplugable PCI BARs there as they won't fit below 4GiB. In addition modern GPGPU devices have very big PCI bars that doesn't fit below 4GiB. The PciHostBridgeLib made lots of assumptions about the coreboot resource allocator that were not verified at runtime and are no longer true. Remove all of the 'coreboot specific' code and implement the same logic as OvmfPkg's ScanForRootBridges. Fixes assertion "ASSERT [PciHostBridgeDxe] Bridge->Mem.Limit < 0x0000000100000000ULL". Tested with coreboot as bootloader on platforms that have PCI resources above 4GiB and on platforms that don't have resources above 4GiB. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> |
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| .. | ||
| PciHostBridge.h | ||
| PciHostBridgeLib.c | ||
| PciHostBridgeLib.inf | ||
| PciHostBridgeSupport.c | ||