audk/CorebootPayloadPkg/Library
Maurice Ma 8a3a97814e CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue
The current PCI 64bit memory BAR size calculation in PciHostBridgeLib
assumes all 32 bits in the upper BAR are fully writable. However,
platform might only support partial address programming, such as 40bit
PCI BAR address. In this case the complement cannot be used for size
calculation.  Instead, the lowest non-zero bit should be used for BAR
size calculation.

Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
2016-05-27 14:28:37 -07:00
..
AcpiTimerLib
PciHostBridgeLib CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue 2016-05-27 14:28:37 -07:00
PlatformBootManagerLib CorebootPayloadPkg: Consume PlatformHookLib in PlatformBootManagerLib 2016-05-23 15:38:37 -07:00
PlatformHookLib CorebootPayloadPkg/PlatformBdsLib: Pass more serial parameters 2016-05-10 10:13:40 -07:00
ResetSystemLib CorebootPayloadPkg: Fix "reset -s" issue. 2015-06-25 16:02:16 +00:00