mirror of https://github.com/acidanthera/audk.git
178 lines
5.1 KiB
NASM
178 lines
5.1 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmiEntry.asm
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;
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; Abstract:
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;
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; Code template of the SMI handler for a particular processor
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;
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;-------------------------------------------------------------------------------
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.686p
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.model flat,C
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.xmm
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DSC_OFFSET EQU 0fb00h
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DSC_GDTPTR EQU 30h
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DSC_GDTSIZ EQU 38h
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DSC_CS EQU 14
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DSC_DS EQU 16
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DSC_SS EQU 18
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DSC_OTHERSEG EQU 20
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PROTECT_MODE_CS EQU 08h
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PROTECT_MODE_DS EQU 20h
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TSS_SEGMENT EQU 40h
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SmiRendezvous PROTO C
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CpuSmmDebugEntry PROTO C
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CpuSmmDebugExit PROTO C
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EXTERNDEF gcSmiHandlerTemplate:BYTE
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EXTERNDEF gcSmiHandlerSize:WORD
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EXTERNDEF gSmiCr3:DWORD
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EXTERNDEF gSmiStack:DWORD
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EXTERNDEF gSmbase:DWORD
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EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
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EXTERNDEF gSmiHandlerIdtr:FWORD
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.code
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gcSmiHandlerTemplate LABEL BYTE
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_SmiEntryPoint:
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DB 0bbh ; mov bx, imm16
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DW offset _GdtDesc - _SmiEntryPoint + 8000h
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DB 2eh, 0a1h ; mov ax, cs:[offset16]
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DW DSC_OFFSET + DSC_GDTSIZ
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dec eax
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mov cs:[edi], eax ; mov cs:[bx], ax
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DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
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DW DSC_OFFSET + DSC_GDTPTR
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mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
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mov bp, ax ; ebp = GDT base
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DB 66h
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lgdt fword ptr cs:[edi] ; lgdt fword ptr cs:[bx]
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; Patch ProtectedMode Segment
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DB 0b8h ; mov ax, imm16
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DW PROTECT_MODE_CS ; set AX for segment directly
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mov cs:[edi - 2], eax ; mov cs:[bx - 2], ax
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; Patch ProtectedMode entry
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DB 66h, 0bfh ; mov edi, SMBASE
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gSmbase DD ?
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DB 67h
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lea ax, [edi + (@32bit - _SmiEntryPoint) + 8000h]
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mov cs:[edi - 6], ax ; mov cs:[bx - 6], eax
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mov ebx, cr0
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DB 66h
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and ebx, 9ffafff3h
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DB 66h
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or ebx, 23h
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mov cr0, ebx
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DB 66h, 0eah
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DD ?
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DW ?
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_GdtDesc FWORD ?
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@32bit:
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mov ax, PROTECT_MODE_DS
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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DB 0bch ; mov esp, imm32
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gSmiStack DD ?
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mov eax, offset gSmiHandlerIdtr
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lidt fword ptr [eax]
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jmp ProtFlatMode
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ProtFlatMode:
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DB 0b8h ; mov eax, imm32
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gSmiCr3 DD ?
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mov cr3, eax
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;
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; Need to test for CR4 specific bit support
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;
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mov eax, 1
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cpuid ; use CPUID to determine if specific CR4 bits are supported
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xor eax, eax ; Clear EAX
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test edx, BIT2 ; Check for DE capabilities
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jz @f
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or eax, BIT3
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@@:
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test edx, BIT6 ; Check for PAE capabilities
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jz @f
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or eax, BIT5
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@@:
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test edx, BIT7 ; Check for MCE capabilities
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jz @f
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or eax, BIT6
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@@:
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test edx, BIT24 ; Check for FXSR capabilities
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jz @f
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or eax, BIT9
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@@:
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test edx, BIT25 ; Check for SSE capabilities
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jz @f
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or eax, BIT10
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@@: ; as cr4.PGE is not set here, refresh cr3
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mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
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mov ebx, cr0
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or ebx, 080010000h ; enable paging + WP
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mov cr0, ebx
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lea ebx, [edi + DSC_OFFSET]
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mov ax, [ebx + DSC_DS]
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mov ds, eax
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mov ax, [ebx + DSC_OTHERSEG]
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mov es, eax
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mov fs, eax
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mov gs, eax
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mov ax, [ebx + DSC_SS]
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mov ss, eax
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cmp FeaturePcdGet (PcdCpuSmmStackGuard), 0
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jz @F
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; Load TSS
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mov byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag
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mov eax, TSS_SEGMENT
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ltr ax
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@@:
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; jmp _SmiHandler ; instruction is not needed
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_SmiHandler PROC
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mov ebx, [esp] ; CPU Index
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push ebx
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mov eax, CpuSmmDebugEntry
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call eax
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pop ecx
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push ebx
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mov eax, SmiRendezvous
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call eax
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pop ecx
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push ebx
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mov eax, CpuSmmDebugExit
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call eax
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pop ecx
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rsm
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_SmiHandler ENDP
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gcSmiHandlerSize DW $ - _SmiEntryPoint
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END
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