Tom Lendacky e674096acc OvmfPkg/ResetVector: Fix assembler bit test flag check ... Commit 63c50d3ff2 changed the check that is used to determine if SEV-ES is active. Originally, a CMP instruction with a supporting JZ instruction was used for the check. It was changed to use the BT instruction but not JZ instruction. The result of a BT instruction changes the the carry flag (CF) and not the zero flag (ZF). As a result, the wrong condition is being checked. Update the JZ to a JNC to properly detect if SEV-ES is active. Fixes: 63c50d3ff2 ("OvmfPkg/ResetVector: cache the SEV status MSR...") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>		2023-07-14 22:52:58 +00:00
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AmdSev.asm	OvmfPkg/ResetVector: Removing SEV-ES CPUID bit check	2022-06-01 12:52:34 +00:00
Flat32ToFlat64.asm	OvmfPkg/ResetVector: Fix assembler bit test flag check	2023-07-14 22:52:58 +00:00
IntelTdx.asm	OvmfPkg: Enable TDX in ResetVector	2021-10-24 02:09:27 +00:00
PageTables64.asm	OvmfPkg: Enable TDX in ResetVector	2021-10-24 02:09:27 +00:00