mirror of https://github.com/acidanthera/audk.git
131 lines
4.1 KiB
NASM
131 lines
4.1 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Transition from 32 bit flat protected mode into 64 bit flat protected mode
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;
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; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 32
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;
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; Modified: EAX, ECX, EDX
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;
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Transition32FlatTo64Flat:
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OneTimeCall SetCr3ForPageTables64
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mov eax, cr4
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bts eax, 5 ; enable PAE
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mov cr4, eax
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;
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; In TDX LME has already been set. So we're done and jump to enable
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; paging directly if Tdx is enabled.
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; EBX is cleared because in the later it will be used to check if
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; the second step of the SEV-ES mitigation is to be performed.
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;
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xor ebx, ebx
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OneTimeCall IsTdxEnabled
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test eax, eax
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jnz EnablePaging
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mov ecx, 0xc0000080
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rdmsr
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bts eax, 8 ; set LME
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wrmsr
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;
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; SEV-ES mitigation check support
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;
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xor ebx, ebx
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mov ecx, 1
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bt [SEV_ES_WORK_AREA_STATUS_MSR], ecx
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jnc EnablePaging
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;
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; SEV-ES is active, perform a quick sanity check against the reported
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; encryption bit position. This is to help mitigate against attacks where
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; the hypervisor reports an incorrect encryption bit position.
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;
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; This is the first step in a two step process. Before paging is enabled
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; writes to memory are encrypted. Using the RDRAND instruction (available
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; on all SEV capable processors), write 64-bits of random data to the
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; SEV_ES_WORK_AREA and maintain the random data in registers (register
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; state is protected under SEV-ES). This will be used in the second step.
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;
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RdRand1:
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rdrand ecx
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jnc RdRand1
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mov dword[SEV_ES_WORK_AREA_RDRAND], ecx
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RdRand2:
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rdrand edx
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jnc RdRand2
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mov dword[SEV_ES_WORK_AREA_RDRAND + 4], edx
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;
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; Use EBX instead of the SEV_ES_WORK_AREA memory to determine whether to
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; perform the second step.
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;
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mov ebx, 1
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EnablePaging:
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mov eax, cr0
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bts eax, 31 ; set PG
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mov cr0, eax ; enable paging
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jmp LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere)
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BITS 64
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jumpTo64BitAndLandHere:
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;
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; Check if the second step of the SEV-ES mitigation is to be performed.
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;
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test ebx, ebx
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jz InsnCompare
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;
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; SEV-ES is active, perform the second step of the encryption bit postion
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; mitigation check. The ECX and EDX register contain data from RDRAND that
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; was stored to memory in encrypted form. If the encryption bit position is
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; valid, the contents of ECX and EDX will match the memory location.
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;
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cmp dword[SEV_ES_WORK_AREA_RDRAND], ecx
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jne SevEncBitHlt
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cmp dword[SEV_ES_WORK_AREA_RDRAND + 4], edx
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jne SevEncBitHlt
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;
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; If SEV or SEV-ES is active, perform a quick sanity check against
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; the reported encryption bit position. This is to help mitigate
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; against attacks where the hypervisor reports an incorrect encryption
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; bit position. If SEV is not active, this check will always succeed.
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;
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; The cmp instruction compares the first four bytes of the cmp instruction
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; itself (which will be read decrypted if SEV or SEV-ES is active and the
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; encryption bit position is valid) against the immediate within the
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; instruction (an instruction fetch is always decrypted correctly by
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; hardware) based on RIP relative addressing.
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;
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InsnCompare:
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cmp dword[rel InsnCompare], 0xFFF63D81
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je GoodCompare
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;
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; The hypervisor provided an incorrect encryption bit position, do not
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; proceed.
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;
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SevEncBitHlt:
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cli
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hlt
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jmp SevEncBitHlt
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GoodCompare:
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debugShowPostCode POSTCODE_64BIT_MODE
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OneTimeCallRet Transition32FlatTo64Flat
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