mirror of https://github.com/acidanthera/audk.git
223 lines
4.8 KiB
NASM
223 lines
4.8 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Intel TDX routines
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;
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; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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%define VM_GUEST_TDX 2
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BITS 32
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;
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; Check if it is Intel Tdx
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;
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; Modified: EAX, EBX, ECX, EDX
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;
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; If it is Intel Tdx, EAX is 1
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; If it is not Intel Tdx, EAX is 0
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;
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IsTdx:
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;
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; CPUID (0)
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;
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mov eax, 0
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cpuid
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cmp ebx, 0x756e6547 ; "Genu"
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jne IsNotTdx
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cmp edx, 0x49656e69 ; "ineI"
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jne IsNotTdx
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cmp ecx, 0x6c65746e ; "ntel"
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jne IsNotTdx
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;
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; CPUID (1)
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;
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mov eax, 1
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cpuid
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test ecx, 0x80000000
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jz IsNotTdx
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;
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; CPUID[0].EAX >= 0x21?
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;
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mov eax, 0
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cpuid
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cmp eax, 0x21
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jl IsNotTdx
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;
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; CPUID (0x21,0)
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;
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mov eax, 0x21
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mov ecx, 0
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cpuid
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cmp ebx, 0x65746E49 ; "Inte"
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jne IsNotTdx
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cmp edx, 0x5844546C ; "lTDX"
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jne IsNotTdx
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cmp ecx, 0x20202020 ; " "
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jne IsNotTdx
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mov eax, 1
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jmp ExitIsTdx
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IsNotTdx:
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xor eax, eax
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ExitIsTdx:
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OneTimeCallRet IsTdx
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;
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; Initialize work area if it is Tdx guest. Detailed definition is in
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; OvmfPkg/Include/WorkArea.h.
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; BSP and APs all go here. Only BSP initialize this work area.
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;
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; Param[in] EBX[5:0] CPU Supported GPAW (48 or 52)
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; Param[in] ESI[31:0] vCPU ID (BSP is 0, others are AP)
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;
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; Modified: EBX
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;
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InitTdxWorkarea:
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;
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; First check if it is Tdx
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;
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OneTimeCall IsTdx
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test eax, eax
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jz ExitInitTdxWorkarea
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cmp esi, 0
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je TdxBspEntry
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;
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; In Td guest, BSP/AP shares the same entry point
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; BSP builds up the page table, while APs shouldn't do the same task.
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; Instead, APs just leverage the page table which is built by BSP.
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; APs will wait until the page table is ready.
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;
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TdxApWait:
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cmp byte[TDX_WORK_AREA_PGTBL_READY], 0
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je TdxApWait
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jmp ExitInitTdxWorkarea
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TdxBspEntry:
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;
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; Set Type of WORK_AREA_GUEST_TYPE so that the following code can use
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; these information.
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;
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mov byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX
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;
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; EBX[5:0] CPU supported GPA width
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;
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and ebx, 0x3f
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mov DWORD[TDX_WORK_AREA_GPAW], ebx
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ExitInitTdxWorkarea:
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OneTimeCallRet InitTdxWorkarea
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;
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; Load the GDT and set the CS/DS/ES/FS/GS/SS.
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;
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; Modified: EAX, DS, ES, FS, GS, SS, CS
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;
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ReloadFlat32:
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cli
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mov eax, ADDR_OF(gdtr)
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lgdt [eax]
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jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpToFlat32BitAndLandHere)
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jumpToFlat32BitAndLandHere:
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debugShowPostCode POSTCODE_32BIT_MODE
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mov ax, LINEAR_SEL
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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OneTimeCallRet ReloadFlat32
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;
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; Tdx initialization after entering into ResetVector
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;
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; Modified: EAX, EBX, ECX, EDX, EBP, EDI, ESP
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;
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InitTdx:
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;
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; First load the GDT and jump to Flat32 mode
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;
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OneTimeCall ReloadFlat32
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;
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; Initialization of Tdx work area
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;
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OneTimeCall InitTdxWorkarea
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OneTimeCallRet InitTdx
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;
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; Check TDX features, TDX or TDX-BSP or TDX-APs?
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;
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; By design TDX BSP is reponsible for initializing the PageTables.
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; After PageTables are ready, byte[TDX_WORK_AREA_PGTBL_READY] is set to 1.
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; APs will spin when byte[TDX_WORK_AREA_PGTBL_READY] is 0 until it is set to 1.
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;
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; When this routine is run on TDX BSP, byte[TDX_WORK_AREA_PGTBL_READY] should be 0.
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; When this routine is run on TDX APs, byte[TDX_WORK_AREA_PGTBL_READY] should be 1.
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;
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;
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; Modified: EAX, EDX
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;
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; 0-NonTdx, 1-TdxBsp, 2-TdxAps
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;
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CheckTdxFeaturesBeforeBuildPagetables:
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xor eax, eax
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cmp byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX
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jne NotTdx
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xor edx, edx
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mov al, byte[TDX_WORK_AREA_PGTBL_READY]
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inc eax
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NotTdx:
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OneTimeCallRet CheckTdxFeaturesBeforeBuildPagetables
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;
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; Set byte[TDX_WORK_AREA_PGTBL_READY] to 1
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;
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TdxPostBuildPageTables:
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cmp byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX
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jne ExitTdxPostBuildPageTables
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mov byte[TDX_WORK_AREA_PGTBL_READY], 1
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ExitTdxPostBuildPageTables:
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OneTimeCallRet TdxPostBuildPageTables
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;
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; Check if TDX is enabled
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;
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; Modified: EAX
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;
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; If TDX is enabled then EAX will be 1
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; If TDX is disabled then EAX will be 0.
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;
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IsTdxEnabled:
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xor eax, eax
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cmp byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX
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jne TdxNotEnabled
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mov eax, 1
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TdxNotEnabled:
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OneTimeCallRet IsTdxEnabled
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