mirror of https://github.com/acidanthera/audk.git
748cd9a680
Within function NvmExpressPassThru(): The data buffer for the below 2 Admin command: Create I/O Completion Queue command (Opcode 01h) Create I/O Submission Queue command (Opcode 05h) are not mapped to the PCI controller specific addresses. But the current code logic also prevents the below NVM command: Write (Opcode 01h) from mapping its data buffer. Hence, this commit refine the logic to resolve this issue. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> |
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| .. | ||
| EhciDxe | ||
| EhciPei | ||
| IdeBusPei | ||
| IncompatiblePciDeviceSupportDxe | ||
| NonDiscoverablePciDeviceDxe | ||
| NvmExpressDxe | ||
| PciBusDxe | ||
| PciHostBridgeDxe | ||
| PciSioSerialDxe | ||
| SataControllerDxe | ||
| SdMmcPciHcDxe | ||
| SdMmcPciHcPei | ||
| UfsPciHcDxe | ||
| UfsPciHcPei | ||
| UhciDxe | ||
| UhciPei | ||
| XhciDxe | ||
| XhciPei | ||