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70023bab7e
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1771 Some buses doesn't allow 8 bit MMIO read/write, this adds support for 32 bits read/write. This patch adds the UNI information on the new Pcd introduced - PcdSerialRegisterAccessWidth Signed-off-by: "Tien Hock, Loh" <tien.hock.loh@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: "Zhu, YongHong" <yonghong.zhu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>