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73dbd6afab
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1167 When the HSEE in the USBCMD bit is a ‘1’ and the HSE bit in the USBSTS register is a ‘1’, the xHC shall assert out-of-band error signaling to the host and assert the SERR# pin. To prevent masking any potential issues with SERR, this patch is to set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is set. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Fei1 Wang <fei1.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>