mirror of https://github.com/acidanthera/audk.git
b2d0e0c51a
Some updates to SCR can cause a problem which manifests as an undefined opcode exception. This may be when a speculative secure instruction fetch happens after the NS bit is set. An isb is required to make the register change take effect fully. Contributed-under: Tianocore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <Evan.Lloyd@arm.com> Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> |
||
|---|---|---|
| .. | ||
| AArch64 | ||
| ArmV7 | ||
| Common | ||
| Null | ||