mirror of https://github.com/acidanthera/audk.git
dd4cae4d82
According to the SBSA specification the Watchdog Compare Register is split into two separate 32bit registers. EDK2 code uses a single 64bit transaction to update them, which can be problematic, depending on the SoC implementation and could result in unpredictable behavior. Fix this by modifying WatchdogWriteCompareRegister routine to use two consecutive 32bit writes to the Watchdog Compare Register Low and High, using new dedicated macros. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> |
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| ArmCrashDumpDxe | ||
| ArmGic | ||
| ArmPciCpuIo2Dxe | ||
| ArmScmiDxe | ||
| CpuDxe | ||
| CpuPei | ||
| GenericWatchdogDxe | ||
| TimerDxe | ||