audk/UefiCpuPkg/PiSmmCpuDxeSmm
Eric Dong 9bae7811d9 UefiCpuPkg/PiSmmCpuDxeSmm: Separate semaphore container.
In current implementation, core and package level sync uses same semaphores.
Sharing the semaphore may cause wrong execution order.
For example:
1. Feature A has CPU_FEATURE_CORE_BEFORE dependency with Feature B.
2. Feature C has CPU_FEATURE_PACKAGE_AFTER dependency with Feature B.
The expected feature initialization order is A B C:
A ---- (Core Depends) ----> B ---- (Package Depends) ----> C

For a CPU has 1 package, 2 cores and 4 threads. The feature initialization
order may like below:

   Thread#1             Thread#2       Thread#3         Thread#4
   [A.Init]             [A.Init]                        [A.Init]
Release(S1, S2)        Release(S1, S2)                Release(S3, S4)
Wait(S1) * 2           Wait(S2) * 2  <------------------------------- Core sync

   [B.Init]             [B.Init]
Release (S1,S2,S3,S4)
Wait (S1) * 4  <----------------------------------------------------- Package sync
                                                      Wait(S4 * 2) <- Core sync
                                                        [B.Init]

In above case, for thread#4, when it syncs in core level, Wait(S4) * 2 isn't
blocked and [B.Init] runs. But [A.Init] hasn't run in thread#3. It's wrong!
Thread#4 should execute [B.Init] after thread#3 executes [A.Init] because B
core level depends on A.

The reason of the wrong execution order is that S4 is released in thread#1
by calling Release (S1, S2, S3, S4) and in thread #4 by calling
Release (S3, S4).

To fix this issue, core level sync and package level sync should use separate
semaphores.

In above example, the S4 released in Release (S1, S2, S3, S4) should not be the
same semaphore as that in Release (S3, S4).

Related BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1311

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2018-11-11 10:02:47 +08:00
..
Ia32 UefiCpuPkg/PiSmmCpuDxeSmm: implement non-stop mode for SMM 2018-08-30 07:22:30 +08:00
X64 UefiCpuPkg/SmmCpu: Block access-out only when static paging is used 2018-11-08 00:13:26 +08:00
CpuS3.c UefiCpuPkg/PiSmmCpuDxeSmm: Separate semaphore container. 2018-11-11 10:02:47 +08:00
CpuService.c UefiCpuPkg/LocalApicLib: Rename GetProcessorLocation() 2016-11-02 09:16:21 +08:00
CpuService.h
MpService.c UefiCpuPkg/PiSmmCpuDxeSmm: Clean up useless code. 2018-10-26 11:28:37 +08:00
PiSmmCpuDxeSmm.c UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5753] Fix bounds check bypass 2018-09-30 13:06:42 +08:00
PiSmmCpuDxeSmm.h UefiCpuPkg/PiSmmCpuDxeSmm: Clean up useless code. 2018-10-26 11:28:37 +08:00
PiSmmCpuDxeSmm.inf UefiCpuPkg PiSmmCpuDxeSmm: Use new EfiLocateFirstAcpiTable() 2018-09-27 14:25:36 +08:00
PiSmmCpuDxeSmm.uni
PiSmmCpuDxeSmmExtra.uni
SmmCpuMemoryManagement.c UefiCpuPkg/PiSmmCpuDxeSmm: Avoid possible NULL ptr dereference 2018-07-31 13:07:47 +08:00
SmmProfile.c UefiCpuPkg PiSmmCpuDxeSmm: Use new EfiLocateFirstAcpiTable() 2018-09-27 14:25:36 +08:00
SmmProfile.h UefiCpuPkg/PiSmmCpuDxeSmm: implement non-stop mode for SMM 2018-08-30 07:22:30 +08:00
SmmProfileInternal.h UefiCpuPkg PiSmmCpuDxeSmm: Use new EfiLocateFirstAcpiTable() 2018-09-27 14:25:36 +08:00
SmramSaveState.c UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86() 2018-04-04 16:44:06 +02:00
SyncTimer.c