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audk/CorebootPayloadPkg
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Maurice Ma 8a3a97814e CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue 
The current PCI 64bit memory BAR size calculation in PciHostBridgeLib
assumes all 32 bits in the upper BAR are fully writable. However,
platform might only support partial address programming, such as 40bit
PCI BAR address. In this case the complement cannot be used for size
calculation.  Instead, the lowest non-zero bit should be used for BAR
size calculation.

Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
 		2016-05-27 14:28:37 -07:00
..
FbGop CorebootPayloadPkg: Switch to use generic BdxDxe driver 2016-05-20 10:11:56 -07:00
Library CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue 2016-05-27 14:28:37 -07:00
BuildAndIntegrationInstructions.txt CorebootPayloadPkg: Rename CorebootPayloadPkgX64.dsc X64 -> Ia32X64 2015-04-14 00:23:17 +00:00
Contributions.txt Coreboot*Pkg/Contributions.txt: Update example email address 2015-04-14 00:23:29 +00:00
CorebootPayloadPkg.dec CorebootPayloadPkg: Add coreboot PlatfromBootManagerLib implementation 2016-05-20 10:11:55 -07:00
CorebootPayloadPkg.fdf CorebootPayloadPkg: Use generic PciBus/PciHostBridge driver 2016-05-23 13:53:41 -07:00
CorebootPayloadPkgIa32.dsc CorebootPayloadPkg: Use generic PciBus/PciHostBridge driver 2016-05-23 13:53:41 -07:00
CorebootPayloadPkgIa32X64.dsc CorebootPayloadPkg: Use generic PciBus/PciHostBridge driver 2016-05-23 13:53:41 -07:00
License.txt
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