mirror of https://github.com/acidanthera/audk.git
Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Appendix A: RVWMO Explanatory Material in https://github.com/riscv/riscv-isa-manual This API is first introduced in the below commits for IA32 and x64 |
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CpuBreakpoint.c | ||
CpuPause.c | ||
CpuScratch.S | ||
DisableInterrupts.c | ||
EnableInterrupts.c | ||
FlushCache.S | ||
GetInterruptState.c | ||
InternalSwitchStack.c | ||
MemoryFence.S | ||
ReadTimer.S | ||
RiscVCpuBreakpoint.S | ||
RiscVCpuPause.S | ||
RiscVInterrupt.S | ||
RiscVMmu.S | ||
RiscVSetJumpLongJump.S | ||
SpeculationBarrier.S |