王洋 0765ee6cd3 MdePkg/BaseLib: Fix boot DxeCore hang on riscv platform ... For scene of HandOffToDxeCore()->SwitchStack(DxeCoreEntryPoint)-> InternalSwitchStack()->LongJump(),Variable HobList.Raw will be passed (from *Context1 to register a0) to DxeMain() in parameter *HobStart. However, meanwhile the function LongJump() overrides register a0 with a1 (-1) due to commit (ea628f28e5 "RISCV: Fix InternalLongJump to return correct value"), then cause hang. Replacing calling LongJump() with new InternalSwitchStackAsm() to pass addres data in register s0 to register a0 could fix this issue (just like the solution in MdePkg/Library/BaseLib/AArch64/SwitchStack.S) Signed-off-by: Yang Wang <wangyang@bosc.ac.cn> Cc: Bamvor Jian ZHANG <zhangjian@bosc.ac.cn> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ran Wang <wangran@bosc.ac.cn> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>		2024-01-11 15:19:26 +00:00
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Include	MdePkg/BaseLib: RISC-V: Add function to update stimecmp register	2024-01-11 12:07:42 +00:00
Library	MdePkg/BaseLib: Fix boot DxeCore hang on riscv platform	2024-01-11 15:19:26 +00:00
Test	MdePkg/Test: Add google tests for BaseLib	2023-12-03 02:37:26 +00:00
MdeLibs.dsc.inc	MdePkg/MdeLibs.dsc.inc: Add SafeIntLib instance	2023-12-20 02:30:56 +00:00
MdePkg.ci.yaml	MdePkg: CI: Add PrEval entry	2023-10-23 20:17:52 +00:00
MdePkg.dec	MdePkg.dec: RISC-V: Define override bit for Sstc extension	2024-01-11 12:07:42 +00:00
MdePkg.dsc	MdePkg: add SBI-based SerialPortLib for RISC-V	2023-05-17 23:47:20 +00:00
MdePkg.uni	MdePkg: Utilize Cache Management Operations Implementation For RISC-V	2023-12-19 12:48:14 +00:00
MdePkgExtra.uni	…