mirror of https://github.com/acidanthera/audk.git
efcc052bdf
The JunoR1 has a GICv2m which is a GICv2 with a little piece of hardware that has some memory mapped locations that can trigger traditional SPI interrupts. This allows some basic PCIe MSI capabilities. Setup the SPI range that is mapped by the MSI window. This range is described in the JunoR1 SoC TRM, table 3-3. Under Interrupt ID 244-351 is described as "GICv2m PCI Express MSI". In the future when these tables are generated programmatically the information may be found in the MSI_TYPER register as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18723 6f19259b-4bc3-4df7-8a09-765794883524 |
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| .. | ||
| AcpiSsdtRootPci.asl | ||
| AcpiTables.inf | ||
| Dsdt.asl | ||
| Facs.aslc | ||
| Fadt.aslc | ||
| Gtdt.aslc | ||
| Madt.aslc | ||