Andrei Warkentin 5bd2e5dfe6 MdePkg: BaseLib: don't log in RISCV InternalSwitchStack ... InternalSwitchStack may be called with a TPL high enough for a DebugLib implementation to assert. Other arch implementations don't log either. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>		2023-03-08 18:10:34 +00:00
..
CpuBreakpoint.c	MdePkg: Apply uncrustify changes	2021-12-07 17:24:28 +00:00
CpuPause.c	MdePkg: Apply uncrustify changes	2021-12-07 17:24:28 +00:00
CpuScratch.S	MdePkg/BaseLib: RISC-V: Add few more helper functions	2023-02-16 05:53:28 +00:00
DisableInterrupts.c	MdePkg: Apply uncrustify changes	2021-12-07 17:24:28 +00:00
EnableInterrupts.c	MdePkg: Apply uncrustify changes	2021-12-07 17:24:28 +00:00
FlushCache.S	MdePkg/BaseLib: BaseLib for RISCV64 architecture	2020-05-07 03:17:15 +00:00
GetInterruptState.c	MdePkg: Apply uncrustify changes	2021-12-07 17:24:28 +00:00
InternalSwitchStack.c	MdePkg: BaseLib: don't log in RISCV InternalSwitchStack	2023-03-08 18:10:34 +00:00
MemoryFence.S	MdePkg/BaseLib: Add MemoryFence implementation for RiscV64	2021-07-21 12:34:13 +00:00
ReadTimer.S	MdePkg/BaseLib: RISC-V: Add few more helper functions	2023-02-16 05:53:28 +00:00
RiscVCpuBreakpoint.S	MdePkg/BaseLib: BaseLib for RISCV64 architecture	2020-05-07 03:17:15 +00:00
RiscVCpuPause.S	MdePkg/BaseLib: BaseLib for RISCV64 architecture	2020-05-07 03:17:15 +00:00
RiscVInterrupt.S	MdePkg/BaseLib: RISC-V: Add few more helper functions	2023-02-16 05:53:28 +00:00
RiscVMmu.S	MdePkg/BaseLib: RISC-V: Add few more helper functions	2023-02-16 05:53:28 +00:00
RiscVSetJumpLongJump.S	MdePkg/BaseLib: BaseLib for RISCV64 architecture	2020-05-07 03:17:15 +00:00