mirror of https://github.com/acidanthera/audk.git
323 lines
7.4 KiB
C
323 lines
7.4 KiB
C
/** @file
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QNC Smm Library Services that implements SMM Region access, S/W SMI generation and detection.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <IntelQNCRegs.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/QNCAccessLib.h>
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#define BOOT_SERVICE_SOFTWARE_SMI_DATA 0
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#define RUNTIME_SOFTWARE_SMI_DATA 1
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/**
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Triggers a run time or boot time SMI.
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This function triggers a software SMM interrupt and set the APMC status with an 8-bit Data.
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@param Data The value to set the APMC status.
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**/
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VOID
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InternalTriggerSmi (
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IN UINT8 Data
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)
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{
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UINT16 PM1BLK_Base;
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UINT16 GPE0BLK_Base;
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UINT32 NewValue;
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//
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// Get PM1BLK_Base & GPE0BLK_Base
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//
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PM1BLK_Base = PcdGet16 (PcdPm1blkIoBaseAddress);
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GPE0BLK_Base = (UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF);
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//
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// Enable APM SMI
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//
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IoOr32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIE), B_QNC_GPE0BLK_SMIE_APM);
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//
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// Enable SMI globally
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//
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NewValue = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);
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NewValue |= SMI_EN;
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QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, NewValue);
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//
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// Set APM_STS
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//
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IoWrite8 (PcdGet16 (PcdSmmDataPort), Data);
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//
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// Generate the APM SMI
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//
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IoWrite8 (PcdGet16 (PcdSmmActivationPort), PcdGet8 (PcdSmmActivationData));
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//
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// Clear the APM SMI Status Bit
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//
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IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), B_QNC_GPE0BLK_SMIS_APM);
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//
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// Set the EOS Bit
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//
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IoOr32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), B_QNC_GPE0BLK_SMIS_EOS);
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}
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/**
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Triggers an SMI at boot time.
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This function triggers a software SMM interrupt at boot time.
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**/
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VOID
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EFIAPI
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TriggerBootServiceSoftwareSmi (
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VOID
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)
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{
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InternalTriggerSmi (BOOT_SERVICE_SOFTWARE_SMI_DATA);
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}
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/**
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Triggers an SMI at run time.
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This function triggers a software SMM interrupt at run time.
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**/
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VOID
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EFIAPI
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TriggerRuntimeSoftwareSmi (
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VOID
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)
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{
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InternalTriggerSmi (RUNTIME_SOFTWARE_SMI_DATA);
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}
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/**
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Gets the software SMI data.
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This function tests if a software SMM interrupt happens. If a software SMI happens,
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it retrieves the SMM data and returns it as a non-negative value; otherwise a negative
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value is returned.
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@return Data The data retrieved from SMM data port in case of a software SMI;
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otherwise a negative value.
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**/
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INTN
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InternalGetSwSmiData (
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VOID
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)
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{
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UINT8 SmiStatus;
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UINT8 Data;
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SmiStatus = IoRead8 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS);
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if (((SmiStatus & B_QNC_GPE0BLK_SMIS_APM) != 0) &&
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(IoRead8 (PcdGet16 (PcdSmmActivationPort)) == PcdGet8 (PcdSmmActivationData))) {
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Data = IoRead8 (PcdGet16 (PcdSmmDataPort));
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return (INTN)(UINTN)Data;
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}
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return -1;
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}
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/**
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Test if a boot time software SMI happened.
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This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and
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it was triggered at boot time, it returns TRUE. Otherwise, it returns FALSE.
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@retval TRUE A software SMI triggered at boot time happened.
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@retval FLASE No software SMI happened or the software SMI was triggered at run time.
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**/
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BOOLEAN
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EFIAPI
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IsBootServiceSoftwareSmi (
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VOID
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)
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{
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return (BOOLEAN) (InternalGetSwSmiData () == BOOT_SERVICE_SOFTWARE_SMI_DATA);
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}
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/**
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Test if a run time software SMI happened.
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This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and
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it was triggered at run time, it returns TRUE. Otherwise, it returns FALSE.
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@retval TRUE A software SMI triggered at run time happened.
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@retval FLASE No software SMI happened or the software SMI was triggered at boot time.
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**/
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BOOLEAN
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EFIAPI
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IsRuntimeSoftwareSmi (
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VOID
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)
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{
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return (BOOLEAN) (InternalGetSwSmiData () == RUNTIME_SOFTWARE_SMI_DATA);
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}
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/**
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Clear APM SMI Status Bit; Set the EOS bit.
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**/
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VOID
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EFIAPI
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ClearSmi (
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VOID
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)
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{
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UINT16 GPE0BLK_Base;
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//
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// Get GpeBase
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//
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GPE0BLK_Base = (UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF);
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//
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// Clear the APM SMI Status Bit
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//
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IoOr16 (GPE0BLK_Base + R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_APM);
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//
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// Set the EOS Bit
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//
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IoOr32 (GPE0BLK_Base + R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_EOS);
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}
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/**
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This routine is the chipset code that accepts a request to "open" a region of SMRAM.
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The region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
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The use of "open" means that the memory is visible from all boot-service
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and SMM agents.
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@retval FALSE Cannot open a locked SMRAM region
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@retval TRUE Success to open SMRAM region.
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**/
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BOOLEAN
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EFIAPI
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QNCOpenSmramRegion (
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VOID
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)
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{
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UINT32 Smram;
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// Read the SMRAM register
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Smram = QncHsmmcRead ();
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//
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// Is the platform locked?
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//
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if (Smram & SMM_LOCKED) {
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// Cannot Open a locked region
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DEBUG ((EFI_D_WARN, "Cannot open a locked SMRAM region\n"));
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return FALSE;
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}
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//
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// Open all SMRAM regions for Host access only
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//
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Smram |= (SMM_WRITE_OPEN | SMM_READ_OPEN); // Open for Host.
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Smram &= ~(NON_HOST_SMM_WR_OPEN | NON_HOST_SMM_RD_OPEN); // Not for others.
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//
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// Write the SMRAM register
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//
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QncHsmmcWrite (Smram);
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return TRUE;
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}
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/**
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This routine is the chipset code that accepts a request to "close" a region of SMRAM.
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The region could be legacy AB or TSEG near top of physical memory.
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The use of "close" means that the memory is only visible from SMM agents,
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not from BS or RT code.
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@retval FALSE Cannot open a locked SMRAM region
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@retval TRUE Success to open SMRAM region.
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**/
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BOOLEAN
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EFIAPI
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QNCCloseSmramRegion (
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VOID
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)
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{
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UINT32 Smram;
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// Read the SMRAM register.
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Smram = QncHsmmcRead ();
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//
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// Is the platform locked?
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//
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if(Smram & SMM_LOCKED) {
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// Cannot Open a locked region
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DEBUG ((EFI_D_WARN, "Cannot close a locked SMRAM region\n"));
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return FALSE;
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}
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Smram &= (~(SMM_WRITE_OPEN | SMM_READ_OPEN | NON_HOST_SMM_WR_OPEN | NON_HOST_SMM_RD_OPEN));
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QncHsmmcWrite (Smram);
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return TRUE;
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}
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/**
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This routine is the chipset code that accepts a request to "lock" SMRAM.
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The region could be legacy AB or TSEG near top of physical memory.
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The use of "lock" means that the memory can no longer be opened
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to BS state.
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**/
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VOID
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EFIAPI
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QNCLockSmramRegion (
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VOID
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)
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{
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UINT32 Smram;
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// Read the SMRAM register.
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Smram = QncHsmmcRead ();
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if(Smram & SMM_LOCKED) {
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DEBUG ((EFI_D_WARN, "SMRAM region already locked!\n"));
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}
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Smram |= SMM_LOCKED;
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QncHsmmcWrite (Smram);
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return;
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}
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