Abner Chang d3abb40d77 MdePkg/Include: RISC-V definitions. ... Add RISC-V processor related definitions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>		2020-05-07 03:17:15 +00:00
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Include	MdePkg/Include: RISC-V definitions.	2020-05-07 03:17:15 +00:00
Library	MdePkg/UefiScsiLib: Set FUA bit for synchronous SCSI Write operations	2020-04-15 01:13:04 +00:00
Test	MdePkg/UnitTestBaseLib: Add check for pointer BinData	2020-03-27 02:03:41 +00:00
MdePkg.ci.yaml	MdeModulePkg: Remove gEfiFormBrowserExProtocolGuid Protocol Guid	2020-03-30 01:13:49 +00:00
MdePkg.dec	MdePkg: Add RISC-V RISCV64 binding	2020-05-07 03:17:15 +00:00
MdePkg.dsc	MdePkg: Add RISC-V RISCV64 binding	2020-05-07 03:17:15 +00:00
MdePkg.uni	MdePkg: Add PcdSpeculationBarrierType	2019-04-30 16:39:09 -07:00
MdePkgExtra.uni	MdePkg: Replace BSD License with BSD+Patent License	2019-04-09 10:58:13 -07:00