mirror of https://github.com/acidanthera/audk.git
e7e89b0861
The original code is using ADMA mode to do clock tuning procedure. It may have problem on some SD/MMC host controllers as there is no way to know when to send next tuning cmd. Update it to PIO mode to strictly follow SD Host Controller Simplified Specification 3.0 Figure 2-29. By this way, if the Buffer Read Ready interrupt is set, we could know it's ok to send the next clock tuning cmd. Cc: Wu, Hao A <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> |
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| EhciDxe | ||
| EhciPei | ||
| IdeBusPei | ||
| IncompatiblePciDeviceSupportDxe | ||
| NvmExpressDxe | ||
| PciBusDxe | ||
| PciHostBridgeDxe | ||
| PciSioSerialDxe | ||
| SdMmcPciHcDxe | ||
| SdMmcPciHcPei | ||
| UfsPciHcDxe | ||
| UfsPciHcPei | ||
| UhciDxe | ||
| UhciPei | ||
| XhciDxe | ||
| XhciPei | ||