mirror of https://github.com/acidanthera/audk.git
8a3a97814e
The current PCI 64bit memory BAR size calculation in PciHostBridgeLib assumes all 32 bits in the upper BAR are fully writable. However, platform might only support partial address programming, such as 40bit PCI BAR address. In this case the complement cannot be used for size calculation. Instead, the lowest non-zero bit should be used for BAR size calculation. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> |
||
|---|---|---|
| .. | ||
| FbGop | ||
| Library | ||
| BuildAndIntegrationInstructions.txt | ||
| Contributions.txt | ||
| CorebootPayloadPkg.dec | ||
| CorebootPayloadPkg.fdf | ||
| CorebootPayloadPkgIa32.dsc | ||
| CorebootPayloadPkgIa32X64.dsc | ||
| License.txt | ||