2009-05-27 23:09:47 +02:00
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/** @file
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CPU DXE Module.
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2011-01-06 03:57:26 +01:00
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Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
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2010-04-24 14:25:26 +02:00
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This program and the accompanying materials
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2009-05-27 23:09:47 +02:00
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CpuDxe.h"
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//
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// Global Variables
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//
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IA32_IDT_GATE_DESCRIPTOR gIdtTable[INTERRUPT_VECTOR_NUMBER] = { 0 };
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EFI_CPU_INTERRUPT_HANDLER ExternalVectorTable[0x100];
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BOOLEAN InterruptState = FALSE;
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EFI_HANDLE mCpuHandle = NULL;
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BOOLEAN mIsFlushingGCD;
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UINT8 mDefaultMemoryType = MTRR_CACHE_WRITE_BACK;
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UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
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UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
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FIXED_MTRR mFixedMtrrTable[] = {
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{
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MTRR_LIB_IA32_MTRR_FIX64K_00000,
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0,
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0x10000
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},
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{
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MTRR_LIB_IA32_MTRR_FIX16K_80000,
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0x80000,
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0x4000
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},
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{
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MTRR_LIB_IA32_MTRR_FIX16K_A0000,
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0xA0000,
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0x4000
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},
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{
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MTRR_LIB_IA32_MTRR_FIX4K_C0000,
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0xC0000,
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0x1000
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},
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{
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MTRR_LIB_IA32_MTRR_FIX4K_C8000,
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0xC8000,
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0x1000
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},
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{
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MTRR_LIB_IA32_MTRR_FIX4K_D0000,
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0xD0000,
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0x1000
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},
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{
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MTRR_LIB_IA32_MTRR_FIX4K_D8000,
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0xD8000,
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0x1000
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},
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{
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MTRR_LIB_IA32_MTRR_FIX4K_E0000,
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0xE0000,
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0x1000
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},
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{
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MTRR_LIB_IA32_MTRR_FIX4K_E8000,
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0xE8000,
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0x1000
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},
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{
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MTRR_LIB_IA32_MTRR_FIX4K_F0000,
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0xF0000,
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0x1000
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},
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{
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MTRR_LIB_IA32_MTRR_FIX4K_F8000,
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0xF8000,
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0x1000
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},
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};
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EFI_CPU_ARCH_PROTOCOL gCpu = {
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CpuFlushCpuDataCache,
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CpuEnableInterrupt,
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CpuDisableInterrupt,
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CpuGetInterruptState,
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CpuInit,
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CpuRegisterInterruptHandler,
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CpuGetTimerValue,
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CpuSetMemoryAttributes,
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1, // NumberOfTimers
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4 // DmaBufferAlignment
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};
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//
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// Error code flag indicating whether or not an error code will be
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// pushed on the stack if an exception occurs.
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//
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// 1 means an error code will be pushed, otherwise 0
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//
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// bit 0 - exception 0
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// bit 1 - exception 1
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// etc.
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//
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UINT32 mErrorCodeFlag = 0x00027d00;
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2010-10-22 03:07:48 +02:00
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//
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// Local function prototypes
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//
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2010-11-01 10:00:23 +01:00
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/**
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Set Interrupt Descriptor Table Handler Address.
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@param Index The Index of the interrupt descriptor table handle.
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@param Handler Handler address.
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**/
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2010-10-22 03:07:48 +02:00
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VOID
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SetInterruptDescriptorTableHandlerAddress (
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IN UINTN Index,
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IN VOID *Handler OPTIONAL
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);
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2009-05-27 23:09:47 +02:00
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//
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// CPU Arch Protocol Functions
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//
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/**
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Common exception handler.
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@param InterruptType Exception type
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@param SystemContext EFI_SYSTEM_CONTEXT
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**/
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VOID
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EFIAPI
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CommonExceptionHandler (
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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#if defined (MDE_CPU_IA32)
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DEBUG ((
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EFI_D_ERROR,
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"!!!! IA32 Exception Type - %08x !!!!\n",
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InterruptType
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));
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2010-07-13 05:08:54 +02:00
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if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {
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2009-05-27 23:09:47 +02:00
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DEBUG ((
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EFI_D_ERROR,
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"ExceptionData - %08x\n",
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SystemContext.SystemContextIa32->ExceptionData
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));
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}
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DEBUG ((
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EFI_D_ERROR,
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"CS - %04x, EIP - %08x, EFL - %08x, SS - %04x\n",
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SystemContext.SystemContextIa32->Cs,
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SystemContext.SystemContextIa32->Eip,
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SystemContext.SystemContextIa32->Eflags,
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SystemContext.SystemContextIa32->Ss
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));
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DEBUG ((
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EFI_D_ERROR,
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"DS - %04x, ES - %04x, FS - %04x, GS - %04x\n",
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SystemContext.SystemContextIa32->Ds,
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SystemContext.SystemContextIa32->Es,
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SystemContext.SystemContextIa32->Fs,
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SystemContext.SystemContextIa32->Gs
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));
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DEBUG ((
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EFI_D_ERROR,
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"EAX - %08x, EBX - %08x, ECX - %08x, EDX - %08x\n",
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SystemContext.SystemContextIa32->Eax,
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SystemContext.SystemContextIa32->Ebx,
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SystemContext.SystemContextIa32->Ecx,
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SystemContext.SystemContextIa32->Edx
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));
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DEBUG ((
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EFI_D_ERROR,
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"ESP - %08x, EBP - %08x, ESI - %08x, EDI - %08x\n",
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SystemContext.SystemContextIa32->Esp,
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SystemContext.SystemContextIa32->Ebp,
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SystemContext.SystemContextIa32->Esi,
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SystemContext.SystemContextIa32->Edi
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));
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DEBUG ((
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EFI_D_ERROR,
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"GDT - %08x LIM - %04x, IDT - %08x LIM - %04x\n",
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SystemContext.SystemContextIa32->Gdtr[0],
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SystemContext.SystemContextIa32->Gdtr[1],
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SystemContext.SystemContextIa32->Idtr[0],
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SystemContext.SystemContextIa32->Idtr[1]
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));
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DEBUG ((
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EFI_D_ERROR,
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"LDT - %08x, TR - %08x\n",
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SystemContext.SystemContextIa32->Ldtr,
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SystemContext.SystemContextIa32->Tr
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));
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DEBUG ((
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EFI_D_ERROR,
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"CR0 - %08x, CR2 - %08x, CR3 - %08x, CR4 - %08x\n",
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SystemContext.SystemContextIa32->Cr0,
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SystemContext.SystemContextIa32->Cr2,
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SystemContext.SystemContextIa32->Cr3,
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SystemContext.SystemContextIa32->Cr4
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));
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DEBUG ((
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EFI_D_ERROR,
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"DR0 - %08x, DR1 - %08x, DR2 - %08x, DR3 - %08x\n",
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SystemContext.SystemContextIa32->Dr0,
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SystemContext.SystemContextIa32->Dr1,
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SystemContext.SystemContextIa32->Dr2,
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SystemContext.SystemContextIa32->Dr3
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));
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DEBUG ((
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EFI_D_ERROR,
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"DR6 - %08x, DR7 - %08x\n",
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SystemContext.SystemContextIa32->Dr6,
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SystemContext.SystemContextIa32->Dr7
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));
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#elif defined (MDE_CPU_X64)
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DEBUG ((
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EFI_D_ERROR,
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"!!!! X64 Exception Type - %016lx !!!!\n",
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(UINT64)InterruptType
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));
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2010-07-13 05:08:54 +02:00
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if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {
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2009-05-27 23:09:47 +02:00
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DEBUG ((
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EFI_D_ERROR,
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"ExceptionData - %016lx\n",
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SystemContext.SystemContextX64->ExceptionData
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));
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}
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DEBUG ((
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EFI_D_ERROR,
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"RIP - %016lx, RFL - %016lx\n",
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SystemContext.SystemContextX64->Rip,
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SystemContext.SystemContextX64->Rflags
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));
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DEBUG ((
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EFI_D_ERROR,
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"RAX - %016lx, RCX - %016lx, RDX - %016lx\n",
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SystemContext.SystemContextX64->Rax,
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SystemContext.SystemContextX64->Rcx,
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SystemContext.SystemContextX64->Rdx
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));
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DEBUG ((
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EFI_D_ERROR,
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"RBX - %016lx, RSP - %016lx, RBP - %016lx\n",
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SystemContext.SystemContextX64->Rbx,
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SystemContext.SystemContextX64->Rsp,
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SystemContext.SystemContextX64->Rbp
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));
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DEBUG ((
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EFI_D_ERROR,
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"RSI - %016lx, RDI - %016lx\n",
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SystemContext.SystemContextX64->Rsi,
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SystemContext.SystemContextX64->Rdi
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));
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DEBUG ((
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EFI_D_ERROR,
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"R8 - %016lx, R9 - %016lx, R10 - %016lx\n",
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SystemContext.SystemContextX64->R8,
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SystemContext.SystemContextX64->R9,
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SystemContext.SystemContextX64->R10
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));
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DEBUG ((
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EFI_D_ERROR,
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"R11 - %016lx, R12 - %016lx, R13 - %016lx\n",
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SystemContext.SystemContextX64->R11,
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SystemContext.SystemContextX64->R12,
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SystemContext.SystemContextX64->R13
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));
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DEBUG ((
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EFI_D_ERROR,
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"R14 - %016lx, R15 - %016lx\n",
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SystemContext.SystemContextX64->R14,
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SystemContext.SystemContextX64->R15
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));
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DEBUG ((
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EFI_D_ERROR,
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"CS - %04lx, DS - %04lx, ES - %04lx, FS - %04lx, GS - %04lx, SS - %04lx\n",
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SystemContext.SystemContextX64->Cs,
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SystemContext.SystemContextX64->Ds,
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SystemContext.SystemContextX64->Es,
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SystemContext.SystemContextX64->Fs,
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SystemContext.SystemContextX64->Gs,
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SystemContext.SystemContextX64->Ss
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));
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DEBUG ((
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EFI_D_ERROR,
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"GDT - %016lx; %04lx, IDT - %016lx; %04lx\n",
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SystemContext.SystemContextX64->Gdtr[0],
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SystemContext.SystemContextX64->Gdtr[1],
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SystemContext.SystemContextX64->Idtr[0],
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SystemContext.SystemContextX64->Idtr[1]
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));
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DEBUG ((
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EFI_D_ERROR,
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"LDT - %016lx, TR - %016lx\n",
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SystemContext.SystemContextX64->Ldtr,
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SystemContext.SystemContextX64->Tr
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));
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DEBUG ((
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EFI_D_ERROR,
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"CR0 - %016lx, CR2 - %016lx, CR3 - %016lx\n",
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SystemContext.SystemContextX64->Cr0,
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SystemContext.SystemContextX64->Cr2,
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SystemContext.SystemContextX64->Cr3
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));
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DEBUG ((
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EFI_D_ERROR,
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"CR4 - %016lx, CR8 - %016lx\n",
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SystemContext.SystemContextX64->Cr4,
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SystemContext.SystemContextX64->Cr8
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));
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DEBUG ((
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EFI_D_ERROR,
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"DR0 - %016lx, DR1 - %016lx, DR2 - %016lx\n",
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SystemContext.SystemContextX64->Dr0,
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SystemContext.SystemContextX64->Dr1,
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SystemContext.SystemContextX64->Dr2
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));
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DEBUG ((
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EFI_D_ERROR,
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"DR3 - %016lx, DR6 - %016lx, DR7 - %016lx\n",
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SystemContext.SystemContextX64->Dr3,
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SystemContext.SystemContextX64->Dr6,
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SystemContext.SystemContextX64->Dr7
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));
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#else
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#error CPU type not supported for exception information dump!
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#endif
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//
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// Hang the system with CpuSleep so the processor will enter a lower power
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// state.
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//
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while (TRUE) {
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CpuSleep ();
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};
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}
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/**
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Flush CPU data cache. If the instruction cache is fully coherent
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with all DMA operations then function can just return EFI_SUCCESS.
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@param This Protocol instance structure
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@param Start Physical address to start flushing from.
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@param Length Number of bytes to flush. Round up to chipset
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granularity.
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@param FlushType Specifies the type of flush operation to perform.
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@retval EFI_SUCCESS If cache was flushed
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@retval EFI_UNSUPPORTED If flush type is not supported.
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@retval EFI_DEVICE_ERROR If requested range could not be flushed.
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**/
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EFI_STATUS
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EFIAPI
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|
|
CpuFlushCpuDataCache (
|
|
|
|
IN EFI_CPU_ARCH_PROTOCOL *This,
|
|
|
|
IN EFI_PHYSICAL_ADDRESS Start,
|
|
|
|
IN UINT64 Length,
|
|
|
|
IN EFI_CPU_FLUSH_TYPE FlushType
|
|
|
|
)
|
|
|
|
{
|
|
|
|
if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
|
|
|
|
AsmWbinvd ();
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
} else if (FlushType == EfiCpuFlushTypeInvalidate) {
|
|
|
|
AsmInvd ();
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
} else {
|
|
|
|
return EFI_UNSUPPORTED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
Enables CPU interrupts.
|
|
|
|
|
|
|
|
@param This Protocol instance structure
|
|
|
|
|
|
|
|
@retval EFI_SUCCESS If interrupts were enabled in the CPU
|
|
|
|
@retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
|
|
|
|
|
|
|
|
**/
|
|
|
|
EFI_STATUS
|
|
|
|
EFIAPI
|
|
|
|
CpuEnableInterrupt (
|
|
|
|
IN EFI_CPU_ARCH_PROTOCOL *This
|
|
|
|
)
|
|
|
|
{
|
|
|
|
EnableInterrupts ();
|
|
|
|
|
|
|
|
InterruptState = TRUE;
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
Disables CPU interrupts.
|
|
|
|
|
|
|
|
@param This Protocol instance structure
|
|
|
|
|
|
|
|
@retval EFI_SUCCESS If interrupts were disabled in the CPU.
|
|
|
|
@retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
|
|
|
|
|
|
|
|
**/
|
|
|
|
EFI_STATUS
|
|
|
|
EFIAPI
|
|
|
|
CpuDisableInterrupt (
|
|
|
|
IN EFI_CPU_ARCH_PROTOCOL *This
|
|
|
|
)
|
|
|
|
{
|
|
|
|
DisableInterrupts ();
|
|
|
|
|
|
|
|
InterruptState = FALSE;
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
Return the state of interrupts.
|
|
|
|
|
|
|
|
@param This Protocol instance structure
|
|
|
|
@param State Pointer to the CPU's current interrupt state
|
|
|
|
|
|
|
|
@retval EFI_SUCCESS If interrupts were disabled in the CPU.
|
|
|
|
@retval EFI_INVALID_PARAMETER State is NULL.
|
|
|
|
|
|
|
|
**/
|
|
|
|
EFI_STATUS
|
|
|
|
EFIAPI
|
|
|
|
CpuGetInterruptState (
|
|
|
|
IN EFI_CPU_ARCH_PROTOCOL *This,
|
|
|
|
OUT BOOLEAN *State
|
|
|
|
)
|
|
|
|
{
|
|
|
|
if (State == NULL) {
|
|
|
|
return EFI_INVALID_PARAMETER;
|
|
|
|
}
|
|
|
|
|
|
|
|
*State = InterruptState;
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
Generates an INIT to the CPU.
|
|
|
|
|
|
|
|
@param This Protocol instance structure
|
|
|
|
@param InitType Type of CPU INIT to perform
|
|
|
|
|
|
|
|
@retval EFI_SUCCESS If CPU INIT occurred. This value should never be
|
|
|
|
seen.
|
|
|
|
@retval EFI_DEVICE_ERROR If CPU INIT failed.
|
|
|
|
@retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
|
|
|
|
|
|
|
|
**/
|
|
|
|
EFI_STATUS
|
|
|
|
EFIAPI
|
|
|
|
CpuInit (
|
|
|
|
IN EFI_CPU_ARCH_PROTOCOL *This,
|
|
|
|
IN EFI_CPU_INIT_TYPE InitType
|
|
|
|
)
|
|
|
|
{
|
|
|
|
return EFI_UNSUPPORTED;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
Registers a function to be called from the CPU interrupt handler.
|
|
|
|
|
|
|
|
@param This Protocol instance structure
|
|
|
|
@param InterruptType Defines which interrupt to hook. IA-32
|
|
|
|
valid range is 0x00 through 0xFF
|
|
|
|
@param InterruptHandler A pointer to a function of type
|
|
|
|
EFI_CPU_INTERRUPT_HANDLER that is called
|
|
|
|
when a processor interrupt occurs. A null
|
|
|
|
pointer is an error condition.
|
|
|
|
|
|
|
|
@retval EFI_SUCCESS If handler installed or uninstalled.
|
|
|
|
@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
|
|
|
|
for InterruptType was previously installed.
|
|
|
|
@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
|
|
|
|
InterruptType was not previously installed.
|
|
|
|
@retval EFI_UNSUPPORTED The interrupt specified by InterruptType
|
|
|
|
is not supported.
|
|
|
|
|
|
|
|
**/
|
|
|
|
EFI_STATUS
|
|
|
|
EFIAPI
|
|
|
|
CpuRegisterInterruptHandler (
|
|
|
|
IN EFI_CPU_ARCH_PROTOCOL *This,
|
|
|
|
IN EFI_EXCEPTION_TYPE InterruptType,
|
|
|
|
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
|
|
|
|
)
|
|
|
|
{
|
|
|
|
if (InterruptType < 0 || InterruptType > 0xff) {
|
|
|
|
return EFI_UNSUPPORTED;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (InterruptHandler == NULL && ExternalVectorTable[InterruptType] == NULL) {
|
|
|
|
return EFI_INVALID_PARAMETER;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (InterruptHandler != NULL && ExternalVectorTable[InterruptType] != NULL) {
|
|
|
|
return EFI_ALREADY_STARTED;
|
|
|
|
}
|
|
|
|
|
2010-10-26 09:52:31 +02:00
|
|
|
SetInterruptDescriptorTableHandlerAddress ((UINTN)InterruptType, NULL);
|
2009-05-27 23:09:47 +02:00
|
|
|
ExternalVectorTable[InterruptType] = InterruptHandler;
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
Returns a timer value from one of the CPU's internal timers. There is no
|
|
|
|
inherent time interval between ticks but is a function of the CPU frequency.
|
|
|
|
|
|
|
|
@param This - Protocol instance structure.
|
|
|
|
@param TimerIndex - Specifies which CPU timer is requested.
|
|
|
|
@param TimerValue - Pointer to the returned timer value.
|
|
|
|
@param TimerPeriod - A pointer to the amount of time that passes
|
|
|
|
in femtoseconds (10-15) for each increment
|
|
|
|
of TimerValue. If TimerValue does not
|
|
|
|
increment at a predictable rate, then 0 is
|
|
|
|
returned. The amount of time that has
|
|
|
|
passed between two calls to GetTimerValue()
|
|
|
|
can be calculated with the formula
|
|
|
|
(TimerValue2 - TimerValue1) * TimerPeriod.
|
|
|
|
This parameter is optional and may be NULL.
|
|
|
|
|
|
|
|
@retval EFI_SUCCESS - If the CPU timer count was returned.
|
|
|
|
@retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
|
|
|
|
@retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
|
|
|
|
@retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
|
|
|
|
|
|
|
|
**/
|
|
|
|
EFI_STATUS
|
|
|
|
EFIAPI
|
|
|
|
CpuGetTimerValue (
|
|
|
|
IN EFI_CPU_ARCH_PROTOCOL *This,
|
|
|
|
IN UINT32 TimerIndex,
|
|
|
|
OUT UINT64 *TimerValue,
|
|
|
|
OUT UINT64 *TimerPeriod OPTIONAL
|
|
|
|
)
|
|
|
|
{
|
|
|
|
if (TimerValue == NULL) {
|
|
|
|
return EFI_INVALID_PARAMETER;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (TimerIndex != 0) {
|
|
|
|
return EFI_INVALID_PARAMETER;
|
|
|
|
}
|
|
|
|
|
|
|
|
*TimerValue = AsmReadTsc ();
|
|
|
|
|
|
|
|
if (TimerPeriod != NULL) {
|
|
|
|
//
|
|
|
|
// BugBug: Hard coded. Don't know how to do this generically
|
|
|
|
//
|
|
|
|
*TimerPeriod = 1000000000;
|
|
|
|
}
|
|
|
|
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
2011-05-24 03:56:29 +02:00
|
|
|
Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
|
|
|
|
|
|
|
|
This function modifies the attributes for the memory region specified by BaseAddress and
|
|
|
|
Length from their current attributes to the attributes specified by Attributes.
|
|
|
|
|
|
|
|
@param This The EFI_CPU_ARCH_PROTOCOL instance.
|
|
|
|
@param BaseAddress The physical address that is the start address of a memory region.
|
|
|
|
@param Length The size in bytes of the memory region.
|
|
|
|
@param Attributes The bit mask of attributes to set for the memory region.
|
|
|
|
|
|
|
|
@retval EFI_SUCCESS The attributes were set for the memory region.
|
|
|
|
@retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
|
|
|
|
BaseAddress and Length cannot be modified.
|
|
|
|
@retval EFI_INVALID_PARAMETER Length is zero.
|
|
|
|
Attributes specified an illegal combination of attributes that
|
|
|
|
cannot be set together.
|
|
|
|
@retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
|
|
|
|
the memory resource range.
|
|
|
|
@retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
|
|
|
|
resource range specified by BaseAddress and Length.
|
|
|
|
The bit mask of attributes is not support for the memory resource
|
|
|
|
range specified by BaseAddress and Length.
|
2009-05-27 23:09:47 +02:00
|
|
|
|
|
|
|
**/
|
|
|
|
EFI_STATUS
|
|
|
|
EFIAPI
|
|
|
|
CpuSetMemoryAttributes (
|
|
|
|
IN EFI_CPU_ARCH_PROTOCOL *This,
|
|
|
|
IN EFI_PHYSICAL_ADDRESS BaseAddress,
|
|
|
|
IN UINT64 Length,
|
|
|
|
IN UINT64 Attributes
|
|
|
|
)
|
|
|
|
{
|
|
|
|
RETURN_STATUS Status;
|
|
|
|
MTRR_MEMORY_CACHE_TYPE CacheType;
|
|
|
|
|
2010-03-10 03:38:39 +01:00
|
|
|
if (!IsMtrrSupported ()) {
|
|
|
|
return EFI_UNSUPPORTED;
|
|
|
|
}
|
|
|
|
|
2009-05-27 23:09:47 +02:00
|
|
|
//
|
|
|
|
// If this function is called because GCD SetMemorySpaceAttributes () is called
|
|
|
|
// by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory
|
|
|
|
// map with MTRR values. So there is no need to modify MTRRs, just return immediately
|
|
|
|
// to avoid unnecessary computing.
|
|
|
|
//
|
|
|
|
if (mIsFlushingGCD) {
|
|
|
|
DEBUG((EFI_D_ERROR, " Flushing GCD\n"));
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (Attributes) {
|
|
|
|
case EFI_MEMORY_UC:
|
|
|
|
CacheType = CacheUncacheable;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case EFI_MEMORY_WC:
|
|
|
|
CacheType = CacheWriteCombining;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case EFI_MEMORY_WT:
|
|
|
|
CacheType = CacheWriteThrough;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case EFI_MEMORY_WP:
|
|
|
|
CacheType = CacheWriteProtected;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case EFI_MEMORY_WB:
|
|
|
|
CacheType = CacheWriteBack;
|
|
|
|
break;
|
|
|
|
|
2011-05-24 03:56:29 +02:00
|
|
|
case EFI_MEMORY_UCE:
|
|
|
|
case EFI_MEMORY_RP:
|
|
|
|
case EFI_MEMORY_XP:
|
|
|
|
case EFI_MEMORY_RUNTIME:
|
2009-05-27 23:09:47 +02:00
|
|
|
return EFI_UNSUPPORTED;
|
2011-05-24 03:56:29 +02:00
|
|
|
|
|
|
|
default:
|
|
|
|
return EFI_INVALID_PARAMETER;
|
2009-05-27 23:09:47 +02:00
|
|
|
}
|
|
|
|
//
|
|
|
|
// call MTRR libary function
|
|
|
|
//
|
2011-01-06 03:57:26 +01:00
|
|
|
Status = MtrrSetMemoryAttribute (
|
2009-05-27 23:09:47 +02:00
|
|
|
BaseAddress,
|
|
|
|
Length,
|
|
|
|
CacheType
|
|
|
|
);
|
|
|
|
|
|
|
|
return (EFI_STATUS) Status;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Initializes the valid bits mask and valid address mask for MTRRs.
|
|
|
|
|
|
|
|
This function initializes the valid bits mask and valid address mask for MTRRs.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
InitializeMtrrMask (
|
|
|
|
VOID
|
|
|
|
)
|
|
|
|
{
|
|
|
|
UINT32 RegEax;
|
|
|
|
UINT8 PhysicalAddressBits;
|
|
|
|
|
|
|
|
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
|
|
|
|
|
|
|
|
if (RegEax >= 0x80000008) {
|
|
|
|
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
|
|
|
|
|
|
|
|
PhysicalAddressBits = (UINT8) RegEax;
|
|
|
|
|
|
|
|
mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
|
|
|
|
mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
|
|
|
|
} else {
|
|
|
|
mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
|
|
|
|
mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2010-07-13 05:08:54 +02:00
|
|
|
Gets GCD Mem Space type from MTRR Type.
|
2009-05-27 23:09:47 +02:00
|
|
|
|
2010-07-13 05:08:54 +02:00
|
|
|
This function gets GCD Mem Space type from MTRR Type.
|
2009-05-27 23:09:47 +02:00
|
|
|
|
2010-07-13 05:08:54 +02:00
|
|
|
@param MtrrAttributes MTRR memory type
|
2009-05-27 23:09:47 +02:00
|
|
|
|
|
|
|
@return GCD Mem Space type
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT64
|
|
|
|
GetMemorySpaceAttributeFromMtrrType (
|
|
|
|
IN UINT8 MtrrAttributes
|
|
|
|
)
|
|
|
|
{
|
|
|
|
switch (MtrrAttributes) {
|
|
|
|
case MTRR_CACHE_UNCACHEABLE:
|
|
|
|
return EFI_MEMORY_UC;
|
|
|
|
case MTRR_CACHE_WRITE_COMBINING:
|
|
|
|
return EFI_MEMORY_WC;
|
|
|
|
case MTRR_CACHE_WRITE_THROUGH:
|
|
|
|
return EFI_MEMORY_WT;
|
|
|
|
case MTRR_CACHE_WRITE_PROTECTED:
|
|
|
|
return EFI_MEMORY_WP;
|
|
|
|
case MTRR_CACHE_WRITE_BACK:
|
|
|
|
return EFI_MEMORY_WB;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Searches memory descriptors covered by given memory range.
|
|
|
|
|
|
|
|
This function searches into the Gcd Memory Space for descriptors
|
|
|
|
(from StartIndex to EndIndex) that contains the memory range
|
|
|
|
specified by BaseAddress and Length.
|
|
|
|
|
|
|
|
@param MemorySpaceMap Gcd Memory Space Map as array.
|
|
|
|
@param NumberOfDescriptors Number of descriptors in map.
|
|
|
|
@param BaseAddress BaseAddress for the requested range.
|
|
|
|
@param Length Length for the requested range.
|
|
|
|
@param StartIndex Start index into the Gcd Memory Space Map.
|
|
|
|
@param EndIndex End index into the Gcd Memory Space Map.
|
|
|
|
|
|
|
|
@retval EFI_SUCCESS Search successfully.
|
|
|
|
@retval EFI_NOT_FOUND The requested descriptors does not exist.
|
|
|
|
|
|
|
|
**/
|
|
|
|
EFI_STATUS
|
|
|
|
SearchGcdMemorySpaces (
|
|
|
|
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
|
|
|
|
IN UINTN NumberOfDescriptors,
|
|
|
|
IN EFI_PHYSICAL_ADDRESS BaseAddress,
|
|
|
|
IN UINT64 Length,
|
|
|
|
OUT UINTN *StartIndex,
|
|
|
|
OUT UINTN *EndIndex
|
|
|
|
)
|
|
|
|
{
|
|
|
|
UINTN Index;
|
|
|
|
|
|
|
|
*StartIndex = 0;
|
|
|
|
*EndIndex = 0;
|
|
|
|
for (Index = 0; Index < NumberOfDescriptors; Index++) {
|
|
|
|
if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
|
|
|
|
BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
|
|
|
|
*StartIndex = Index;
|
|
|
|
}
|
|
|
|
if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
|
|
|
|
BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
|
|
|
|
*EndIndex = Index;
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return EFI_NOT_FOUND;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Sets the attributes for a specified range in Gcd Memory Space Map.
|
|
|
|
|
|
|
|
This function sets the attributes for a specified range in
|
|
|
|
Gcd Memory Space Map.
|
|
|
|
|
|
|
|
@param MemorySpaceMap Gcd Memory Space Map as array
|
|
|
|
@param NumberOfDescriptors Number of descriptors in map
|
|
|
|
@param BaseAddress BaseAddress for the range
|
|
|
|
@param Length Length for the range
|
|
|
|
@param Attributes Attributes to set
|
|
|
|
|
|
|
|
@retval EFI_SUCCESS Memory attributes set successfully
|
|
|
|
@retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
|
|
|
|
|
|
|
|
**/
|
|
|
|
EFI_STATUS
|
|
|
|
SetGcdMemorySpaceAttributes (
|
|
|
|
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
|
|
|
|
IN UINTN NumberOfDescriptors,
|
|
|
|
IN EFI_PHYSICAL_ADDRESS BaseAddress,
|
|
|
|
IN UINT64 Length,
|
|
|
|
IN UINT64 Attributes
|
|
|
|
)
|
|
|
|
{
|
|
|
|
EFI_STATUS Status;
|
|
|
|
UINTN Index;
|
|
|
|
UINTN StartIndex;
|
|
|
|
UINTN EndIndex;
|
|
|
|
EFI_PHYSICAL_ADDRESS RegionStart;
|
|
|
|
UINT64 RegionLength;
|
|
|
|
|
|
|
|
//
|
|
|
|
// Get all memory descriptors covered by the memory range
|
|
|
|
//
|
|
|
|
Status = SearchGcdMemorySpaces (
|
|
|
|
MemorySpaceMap,
|
|
|
|
NumberOfDescriptors,
|
|
|
|
BaseAddress,
|
|
|
|
Length,
|
|
|
|
&StartIndex,
|
|
|
|
&EndIndex
|
|
|
|
);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
|
|
return Status;
|
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
// Go through all related descriptors and set attributes accordingly
|
|
|
|
//
|
|
|
|
for (Index = StartIndex; Index <= EndIndex; Index++) {
|
|
|
|
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
//
|
|
|
|
// Calculate the start and end address of the overlapping range
|
|
|
|
//
|
|
|
|
if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
|
|
|
|
RegionStart = BaseAddress;
|
|
|
|
} else {
|
|
|
|
RegionStart = MemorySpaceMap[Index].BaseAddress;
|
|
|
|
}
|
|
|
|
if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
|
|
|
|
RegionLength = BaseAddress + Length - RegionStart;
|
|
|
|
} else {
|
|
|
|
RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
|
|
|
|
}
|
|
|
|
//
|
|
|
|
// Set memory attributes according to MTRR attribute and the original attribute of descriptor
|
|
|
|
//
|
|
|
|
gDS->SetMemorySpaceAttributes (
|
|
|
|
RegionStart,
|
|
|
|
RegionLength,
|
|
|
|
(MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
|
|
|
|
);
|
|
|
|
}
|
|
|
|
|
|
|
|
return EFI_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
Refreshes the GCD Memory Space attributes according to MTRRs.
|
|
|
|
|
|
|
|
This function refreshes the GCD Memory Space attributes according to MTRRs.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
RefreshGcdMemoryAttributes (
|
|
|
|
VOID
|
|
|
|
)
|
|
|
|
{
|
|
|
|
EFI_STATUS Status;
|
|
|
|
UINTN Index;
|
|
|
|
UINTN SubIndex;
|
|
|
|
UINT64 RegValue;
|
|
|
|
EFI_PHYSICAL_ADDRESS BaseAddress;
|
|
|
|
UINT64 Length;
|
|
|
|
UINT64 Attributes;
|
|
|
|
UINT64 CurrentAttributes;
|
|
|
|
UINT8 MtrrType;
|
|
|
|
UINTN NumberOfDescriptors;
|
|
|
|
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
|
|
|
|
UINT64 DefaultAttributes;
|
2010-02-10 18:37:37 +01:00
|
|
|
VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
|
2009-05-27 23:09:47 +02:00
|
|
|
MTRR_FIXED_SETTINGS MtrrFixedSettings;
|
2010-02-05 07:33:42 +01:00
|
|
|
UINT32 FirmwareVariableMtrrCount;
|
|
|
|
|
2010-03-10 03:38:39 +01:00
|
|
|
if (!IsMtrrSupported ()) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-02-05 07:33:42 +01:00
|
|
|
FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
|
2010-03-04 07:38:22 +01:00
|
|
|
ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
|
2009-05-27 23:09:47 +02:00
|
|
|
|
|
|
|
// mIsFlushingGCD = TRUE;
|
|
|
|
mIsFlushingGCD = FALSE;
|
|
|
|
MemorySpaceMap = NULL;
|
|
|
|
|
|
|
|
//
|
|
|
|
// Initialize the valid bits mask and valid address mask for MTRRs
|
|
|
|
//
|
|
|
|
InitializeMtrrMask ();
|
|
|
|
|
|
|
|
//
|
|
|
|
// Get the memory attribute of variable MTRRs
|
|
|
|
//
|
|
|
|
MtrrGetMemoryAttributeInVariableMtrr (
|
|
|
|
mValidMtrrBitsMask,
|
|
|
|
mValidMtrrAddressMask,
|
|
|
|
VariableMtrr
|
|
|
|
);
|
|
|
|
|
|
|
|
//
|
|
|
|
// Get the memory space map from GCD
|
|
|
|
//
|
|
|
|
Status = gDS->GetMemorySpaceMap (
|
|
|
|
&NumberOfDescriptors,
|
|
|
|
&MemorySpaceMap
|
|
|
|
);
|
|
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
|
|
|
|
DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (mDefaultMemoryType);
|
|
|
|
|
|
|
|
//
|
|
|
|
// Set default attributes to all spaces.
|
|
|
|
//
|
|
|
|
for (Index = 0; Index < NumberOfDescriptors; Index++) {
|
|
|
|
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
gDS->SetMemorySpaceAttributes (
|
|
|
|
MemorySpaceMap[Index].BaseAddress,
|
|
|
|
MemorySpaceMap[Index].Length,
|
|
|
|
(MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |
|
|
|
|
(MemorySpaceMap[Index].Capabilities & DefaultAttributes)
|
|
|
|
);
|
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
// Go for variable MTRRs with WB attribute
|
|
|
|
//
|
2010-02-05 07:33:42 +01:00
|
|
|
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
|
2009-05-27 23:09:47 +02:00
|
|
|
if (VariableMtrr[Index].Valid &&
|
|
|
|
VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {
|
|
|
|
SetGcdMemorySpaceAttributes (
|
|
|
|
MemorySpaceMap,
|
|
|
|
NumberOfDescriptors,
|
|
|
|
VariableMtrr[Index].BaseAddress,
|
|
|
|
VariableMtrr[Index].Length,
|
|
|
|
EFI_MEMORY_WB
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
//
|
|
|
|
// Go for variable MTRRs with Non-WB attribute
|
|
|
|
//
|
2010-02-05 07:33:42 +01:00
|
|
|
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
|
2009-05-27 23:09:47 +02:00
|
|
|
if (VariableMtrr[Index].Valid &&
|
|
|
|
VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) {
|
|
|
|
Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);
|
|
|
|
SetGcdMemorySpaceAttributes (
|
|
|
|
MemorySpaceMap,
|
|
|
|
NumberOfDescriptors,
|
|
|
|
VariableMtrr[Index].BaseAddress,
|
|
|
|
VariableMtrr[Index].Length,
|
|
|
|
Attributes
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
// Go for fixed MTRRs
|
|
|
|
//
|
|
|
|
Attributes = 0;
|
|
|
|
BaseAddress = 0;
|
|
|
|
Length = 0;
|
|
|
|
MtrrGetFixedMtrr (&MtrrFixedSettings);
|
|
|
|
for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
|
|
|
|
RegValue = MtrrFixedSettings.Mtrr[Index];
|
|
|
|
//
|
|
|
|
// Check for continuous fixed MTRR sections
|
|
|
|
//
|
|
|
|
for (SubIndex = 0; SubIndex < 8; SubIndex++) {
|
|
|
|
MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);
|
|
|
|
CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
|
|
|
|
if (Length == 0) {
|
|
|
|
//
|
|
|
|
// A new MTRR attribute begins
|
|
|
|
//
|
|
|
|
Attributes = CurrentAttributes;
|
|
|
|
} else {
|
|
|
|
//
|
|
|
|
// If fixed MTRR attribute changed, then set memory attribute for previous atrribute
|
|
|
|
//
|
|
|
|
if (CurrentAttributes != Attributes) {
|
|
|
|
SetGcdMemorySpaceAttributes (
|
|
|
|
MemorySpaceMap,
|
|
|
|
NumberOfDescriptors,
|
|
|
|
BaseAddress,
|
|
|
|
Length,
|
|
|
|
Attributes
|
|
|
|
);
|
|
|
|
BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;
|
|
|
|
Length = 0;
|
|
|
|
Attributes = CurrentAttributes;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
Length += mFixedMtrrTable[Index].Length;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
//
|
|
|
|
// Handle the last fixed MTRR region
|
|
|
|
//
|
|
|
|
SetGcdMemorySpaceAttributes (
|
|
|
|
MemorySpaceMap,
|
|
|
|
NumberOfDescriptors,
|
|
|
|
BaseAddress,
|
|
|
|
Length,
|
|
|
|
Attributes
|
|
|
|
);
|
|
|
|
|
|
|
|
//
|
|
|
|
// Free memory space map allocated by GCD service GetMemorySpaceMap ()
|
|
|
|
//
|
|
|
|
if (MemorySpaceMap != NULL) {
|
|
|
|
FreePool (MemorySpaceMap);
|
|
|
|
}
|
|
|
|
|
|
|
|
mIsFlushingGCD = FALSE;
|
|
|
|
}
|
|
|
|
|
2010-11-01 10:00:23 +01:00
|
|
|
/**
|
|
|
|
Set Interrupt Descriptor Table Handler Address.
|
|
|
|
|
|
|
|
@param Index The Index of the interrupt descriptor table handle.
|
|
|
|
@param Handler Handler address.
|
2009-05-27 23:09:47 +02:00
|
|
|
|
2010-11-01 10:00:23 +01:00
|
|
|
**/
|
2010-10-22 03:07:48 +02:00
|
|
|
VOID
|
|
|
|
SetInterruptDescriptorTableHandlerAddress (
|
|
|
|
IN UINTN Index,
|
|
|
|
IN VOID *Handler OPTIONAL
|
|
|
|
)
|
|
|
|
{
|
|
|
|
UINTN UintnHandler;
|
|
|
|
|
|
|
|
if (Handler != NULL) {
|
|
|
|
UintnHandler = (UINTN) Handler;
|
|
|
|
} else {
|
|
|
|
UintnHandler = ((UINTN) AsmIdtVector00) + (8 * Index);
|
|
|
|
}
|
|
|
|
|
|
|
|
gIdtTable[Index].Bits.OffsetLow = (UINT16)UintnHandler;
|
|
|
|
gIdtTable[Index].Bits.Reserved_0 = 0;
|
|
|
|
gIdtTable[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
|
|
|
|
gIdtTable[Index].Bits.OffsetHigh = (UINT16)(UintnHandler >> 16);
|
|
|
|
#if defined (MDE_CPU_X64)
|
|
|
|
gIdtTable[Index].Bits.OffsetUpper = (UINT32)(UintnHandler >> 32);
|
|
|
|
gIdtTable[Index].Bits.Reserved_1 = 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-05-27 23:09:47 +02:00
|
|
|
/**
|
|
|
|
Initialize Interrupt Descriptor Table for interrupt handling.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
InitInterruptDescriptorTable (
|
|
|
|
VOID
|
|
|
|
)
|
|
|
|
{
|
2010-10-22 03:07:48 +02:00
|
|
|
EFI_STATUS Status;
|
|
|
|
IA32_DESCRIPTOR OldIdtPtr;
|
|
|
|
IA32_IDT_GATE_DESCRIPTOR *OldIdt;
|
|
|
|
UINTN OldIdtSize;
|
|
|
|
VOID *IdtPtrAlignmentBuffer;
|
|
|
|
IA32_DESCRIPTOR *IdtPtr;
|
|
|
|
UINTN Index;
|
|
|
|
UINT16 CurrentCs;
|
|
|
|
VOID *IntHandler;
|
2009-05-27 23:09:47 +02:00
|
|
|
|
|
|
|
SetMem (ExternalVectorTable, sizeof(ExternalVectorTable), 0);
|
|
|
|
|
|
|
|
//
|
2010-10-22 03:07:48 +02:00
|
|
|
// Get original IDT address and size.
|
2009-05-27 23:09:47 +02:00
|
|
|
//
|
2010-10-22 03:07:48 +02:00
|
|
|
AsmReadIdtr ((IA32_DESCRIPTOR *) &OldIdtPtr);
|
|
|
|
|
|
|
|
if ((OldIdtPtr.Base != 0) && ((OldIdtPtr.Limit & 7) == 7)) {
|
|
|
|
OldIdt = (IA32_IDT_GATE_DESCRIPTOR*) OldIdtPtr.Base;
|
2010-12-17 03:38:26 +01:00
|
|
|
OldIdtSize = (OldIdtPtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
|
2010-10-22 03:07:48 +02:00
|
|
|
} else {
|
|
|
|
OldIdt = NULL;
|
|
|
|
OldIdtSize = 0;
|
2009-05-27 23:09:47 +02:00
|
|
|
}
|
|
|
|
|
2010-08-03 06:54:44 +02:00
|
|
|
//
|
2010-10-22 03:07:48 +02:00
|
|
|
// Intialize IDT
|
2010-08-03 06:54:44 +02:00
|
|
|
//
|
2010-10-22 03:07:48 +02:00
|
|
|
CurrentCs = AsmReadCs();
|
|
|
|
for (Index = 0; Index < INTERRUPT_VECTOR_NUMBER; Index ++) {
|
|
|
|
//
|
|
|
|
// If the old IDT had a handler for this interrupt, then
|
|
|
|
// preserve it.
|
|
|
|
//
|
|
|
|
if (Index < OldIdtSize) {
|
|
|
|
IntHandler =
|
|
|
|
(VOID*) (
|
|
|
|
OldIdt[Index].Bits.OffsetLow +
|
|
|
|
(OldIdt[Index].Bits.OffsetHigh << 16)
|
|
|
|
#if defined (MDE_CPU_X64)
|
|
|
|
+ (((UINTN) OldIdt[Index].Bits.OffsetUpper) << 32)
|
|
|
|
#endif
|
|
|
|
);
|
|
|
|
} else {
|
|
|
|
IntHandler = NULL;
|
|
|
|
}
|
2010-08-03 06:54:44 +02:00
|
|
|
|
2010-10-22 03:07:48 +02:00
|
|
|
gIdtTable[Index].Bits.Selector = CurrentCs;
|
|
|
|
gIdtTable[Index].Bits.Reserved_0 = 0;
|
|
|
|
gIdtTable[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
|
|
|
|
SetInterruptDescriptorTableHandlerAddress (Index, IntHandler);
|
2010-08-03 06:54:44 +02:00
|
|
|
}
|
2010-10-22 03:07:48 +02:00
|
|
|
|
2009-05-27 23:09:47 +02:00
|
|
|
//
|
|
|
|
// Load IDT Pointer
|
|
|
|
//
|
|
|
|
IdtPtrAlignmentBuffer = AllocatePool (sizeof (*IdtPtr) + 16);
|
|
|
|
IdtPtr = ALIGN_POINTER (IdtPtrAlignmentBuffer, 16);
|
|
|
|
IdtPtr->Base = (UINT32)(((UINTN)(VOID*) gIdtTable) & (BASE_4GB-1));
|
2010-08-10 08:57:32 +02:00
|
|
|
IdtPtr->Limit = (UINT16) (sizeof (gIdtTable) - 1);
|
2010-02-09 10:23:17 +01:00
|
|
|
|
2009-05-27 23:09:47 +02:00
|
|
|
AsmWriteIdtr (IdtPtr);
|
2010-02-09 10:23:17 +01:00
|
|
|
|
2009-05-27 23:09:47 +02:00
|
|
|
FreePool (IdtPtrAlignmentBuffer);
|
|
|
|
|
|
|
|
//
|
|
|
|
// Initialize Exception Handlers
|
|
|
|
//
|
2011-05-25 04:35:34 +02:00
|
|
|
for (Index = OldIdtSize; Index < 32; Index++) {
|
2009-05-27 23:09:47 +02:00
|
|
|
Status = CpuRegisterInterruptHandler (&gCpu, Index, CommonExceptionHandler);
|
|
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
}
|
|
|
|
|
|
|
|
//
|
|
|
|
// Set the pointer to the array of C based exception handling routines.
|
|
|
|
//
|
|
|
|
InitializeExternalVectorTablePtr (ExternalVectorTable);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
Initialize the state information for the CPU Architectural Protocol.
|
|
|
|
|
|
|
|
@param ImageHandle Image handle this driver.
|
|
|
|
@param SystemTable Pointer to the System Table.
|
|
|
|
|
|
|
|
@retval EFI_SUCCESS Thread can be successfully created
|
|
|
|
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
|
|
|
|
@retval EFI_DEVICE_ERROR Cannot create the thread
|
|
|
|
|
|
|
|
**/
|
|
|
|
EFI_STATUS
|
|
|
|
EFIAPI
|
|
|
|
InitializeCpu (
|
|
|
|
IN EFI_HANDLE ImageHandle,
|
|
|
|
IN EFI_SYSTEM_TABLE *SystemTable
|
|
|
|
)
|
|
|
|
{
|
|
|
|
EFI_STATUS Status;
|
|
|
|
|
|
|
|
//
|
|
|
|
// Make sure interrupts are disabled
|
|
|
|
//
|
|
|
|
DisableInterrupts ();
|
|
|
|
|
|
|
|
//
|
|
|
|
// Init GDT for DXE
|
|
|
|
//
|
|
|
|
InitGlobalDescriptorTable ();
|
|
|
|
|
|
|
|
//
|
|
|
|
// Setup IDT pointer, IDT and interrupt entry points
|
|
|
|
//
|
|
|
|
InitInterruptDescriptorTable ();
|
|
|
|
|
|
|
|
//
|
|
|
|
// Install CPU Architectural Protocol
|
|
|
|
//
|
|
|
|
Status = gBS->InstallMultipleProtocolInterfaces (
|
|
|
|
&mCpuHandle,
|
|
|
|
&gEfiCpuArchProtocolGuid, &gCpu,
|
|
|
|
NULL
|
|
|
|
);
|
|
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
|
|
|
|
//
|
|
|
|
// Refresh GCD memory space map according to MTRR value.
|
|
|
|
//
|
|
|
|
RefreshGcdMemoryAttributes ();
|
|
|
|
|
|
|
|
return Status;
|
|
|
|
}
|
|
|
|
|