mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmCortexA5x: Declared the helper functions to access the CPU Extended Control Register
This register is A5x specific. It is the reason why the code moved from ArmLib to ArmCpuLib/ArmCortexA5xLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15397 6f19259b-4bc3-4df7-8a09-765794883524
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@ -0,0 +1,32 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2013 - 2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLibV8.h>
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.text
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.align 3
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GCC_ASM_EXPORT (ArmReadCpuExCr)
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GCC_ASM_EXPORT (ArmWriteCpuExCr)
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ASM_PFX(ArmReadCpuExCr):
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mrs x0, S3_1_c15_c2_1
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ret
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ASM_PFX(ArmWriteCpuExCr):
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msr S3_1_c15_c2_1, x0
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dsb sy
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isb
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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@ -48,3 +48,27 @@ ArmCpuSetupSmpNonSecure (
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)
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)
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{
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{
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}
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}
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VOID
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EFIAPI
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ArmSetCpuExCrBit (
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IN UINT64 Bits
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)
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{
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UINT64 Value;
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Value = ArmReadCpuExCr ();
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Value |= Bits;
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ArmWriteCpuExCr (Value);
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}
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VOID
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EFIAPI
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ArmUnsetCpuExCrBit (
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IN UINT64 Bits
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)
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{
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UINT64 Value;
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Value = ArmReadCpuExCr ();
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Value &= ~Bits;
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ArmWriteCpuExCr (Value);
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}
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@ -1,5 +1,5 @@
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#/* @file
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#/* @file
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# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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#
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#
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# This program and the accompanying materials
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# are licensed and made available under the terms and conditions of the BSD License
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@ -31,5 +31,8 @@
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[Sources.common]
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[Sources.common]
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ArmCortexA5xLib.c
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ArmCortexA5xLib.c
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[Sources.AARCH64]
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AArch64/ArmCortexA5xHelper.S | GCC
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[FixedPcd]
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
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@ -1,6 +1,6 @@
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/** @file
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/** @file
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Copyright (c) 2012-2013, ARM Limited. All rights reserved.
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Copyright (c) 2012-2014, ARM Limited. All rights reserved.
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This program and the accompanying materials
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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are licensed and made available under the terms and conditions of the BSD License
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@ -20,4 +20,31 @@
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//
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//
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#define A5X_FEATURE_SMP (1 << 6)
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#define A5X_FEATURE_SMP (1 << 6)
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//
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// Helper functions to access CPU Extended Control Register
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//
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UINT64
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EFIAPI
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ArmReadCpuExCr (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCpuExCr (
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IN UINT64 Val
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);
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VOID
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EFIAPI
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ArmSetCpuExCrBit (
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IN UINT64 Bits
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);
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VOID
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EFIAPI
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ArmUnsetCpuExCrBit (
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IN UINT64 Bits
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);
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#endif
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#endif
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@ -37,8 +37,6 @@ GCC_ASM_EXPORT (ArmWriteScr)
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GCC_ASM_EXPORT (ArmWriteMVBar)
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GCC_ASM_EXPORT (ArmWriteMVBar)
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GCC_ASM_EXPORT (ArmCallWFE)
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GCC_ASM_EXPORT (ArmCallWFE)
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GCC_ASM_EXPORT (ArmCallSEV)
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GCC_ASM_EXPORT (ArmCallSEV)
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GCC_ASM_EXPORT (ArmReadCpuExCr)
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GCC_ASM_EXPORT (ArmWriteCpuExCr)
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GCC_ASM_EXPORT (ArmReadCpuActlr)
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GCC_ASM_EXPORT (ArmReadCpuActlr)
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GCC_ASM_EXPORT (ArmWriteCpuActlr)
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GCC_ASM_EXPORT (ArmWriteCpuActlr)
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@ -200,16 +198,6 @@ ASM_PFX(ArmCallSEV):
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sev
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sev
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ret
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ret
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ASM_PFX(ArmReadCpuExCr):
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mrs x0, S3_1_c15_c2_1
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ret
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ASM_PFX(ArmWriteCpuExCr):
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msr S3_1_c15_c2_1, x0
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dsb sy
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isb
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ret
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ASM_PFX(ArmReadCpuActlr):
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ASM_PFX(ArmReadCpuActlr):
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mrs x0, S3_1_c15_c2_0
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mrs x0, S3_1_c15_c2_0
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ret
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ret
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