mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1946
The patch changes SMM environment to use 5 level paging when CPU
supports it.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
(cherry picked from commit 7365eb2c8c)
This commit is contained in:
Ray Ni
parent
6e5a33d1fb
commit
4eee0cc7cc
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@ -125,18 +125,36 @@ GetPageTableEntry (
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UINTN Index2;
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UINTN Index3;
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UINTN Index4;
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UINTN Index5;
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UINT64 *L1PageTable;
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UINT64 *L2PageTable;
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UINT64 *L3PageTable;
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UINT64 *L4PageTable;
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UINT64 *L5PageTable;
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IA32_CR4 Cr4;
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BOOLEAN Enable5LevelPaging;
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Index5 = ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK;
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Index4 = ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK;
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Index3 = ((UINTN)Address >> 30) & PAGING_PAE_INDEX_MASK;
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Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;
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Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;
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Cr4.UintN = AsmReadCr4 ();
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Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
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if (sizeof(UINTN) == sizeof(UINT64)) {
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if (Enable5LevelPaging) {
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L5PageTable = (UINT64 *)GetPageTableBase ();
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if (L5PageTable[Index5] == 0) {
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*PageAttribute = PageNone;
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return NULL;
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}
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L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
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} else {
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L4PageTable = (UINT64 *)GetPageTableBase ();
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}
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if (L4PageTable[Index4] == 0) {
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*PageAttribute = PageNone;
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return NULL;
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@ -534,34 +534,62 @@ InitPaging (
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VOID
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)
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{
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UINT64 Pml5Entry;
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UINT64 Pml4Entry;
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UINT64 *Pml5;
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UINT64 *Pml4;
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UINT64 *Pdpt;
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UINT64 *Pd;
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UINT64 *Pt;
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UINTN Address;
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UINTN Pml5Index;
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UINTN Pml4Index;
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UINTN PdptIndex;
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UINTN PdIndex;
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UINTN PtIndex;
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UINTN NumberOfPdptEntries;
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UINTN NumberOfPml4Entries;
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UINTN NumberOfPml5Entries;
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UINTN SizeOfMemorySpace;
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BOOLEAN Nx;
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IA32_CR4 Cr4;
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BOOLEAN Enable5LevelPaging;
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Cr4.UintN = AsmReadCr4 ();
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Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
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if (sizeof (UINTN) == sizeof (UINT64)) {
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Pml4 = (UINT64*)(UINTN)mSmmProfileCr3;
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if (!Enable5LevelPaging) {
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Pml5Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P;
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Pml5 = &Pml5Entry;
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} else {
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Pml5 = (UINT64*) (UINTN) mSmmProfileCr3;
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}
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SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1;
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//
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// Calculate the table entries of PML4E and PDPTE.
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//
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if (SizeOfMemorySpace <= 39 ) {
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NumberOfPml4Entries = 1;
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NumberOfPdptEntries = (UINT32)LShiftU64 (1, (SizeOfMemorySpace - 30));
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} else {
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NumberOfPml4Entries = (UINT32)LShiftU64 (1, (SizeOfMemorySpace - 39));
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NumberOfPdptEntries = 512;
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NumberOfPml5Entries = 1;
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if (SizeOfMemorySpace > 48) {
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NumberOfPml5Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 48);
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SizeOfMemorySpace = 48;
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}
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NumberOfPml4Entries = 1;
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if (SizeOfMemorySpace > 39) {
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NumberOfPml4Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 39);
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SizeOfMemorySpace = 39;
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}
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NumberOfPdptEntries = 1;
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ASSERT (SizeOfMemorySpace > 30);
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NumberOfPdptEntries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 30);
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} else {
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Pml4Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P;
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Pml4 = &Pml4Entry;
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Pml5Entry = (UINTN) Pml4 | IA32_PG_P;
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Pml5 = &Pml5Entry;
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NumberOfPml5Entries = 1;
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NumberOfPml4Entries = 1;
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NumberOfPdptEntries = 4;
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}
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@ -569,8 +597,15 @@ InitPaging (
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//
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// Go through page table and change 2MB-page into 4KB-page.
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//
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for (Pml5Index = 0; Pml5Index < NumberOfPml5Entries; Pml5Index++) {
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if ((Pml5[Pml5Index] & IA32_PG_P) == 0) {
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//
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// If PML5 entry does not exist, skip it
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//
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continue;
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}
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Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
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for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {
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if (sizeof (UINTN) == sizeof (UINT64)) {
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if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {
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//
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// If PML4 entry does not exist, skip it
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@ -578,9 +613,6 @@ InitPaging (
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continue;
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}
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Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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} else {
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Pdpt = (UINT64*)(UINTN)mSmmProfileCr3;
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}
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for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {
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if ((*Pdpt & IA32_PG_P) == 0) {
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//
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@ -605,7 +637,13 @@ InitPaging (
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//
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continue;
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}
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Address = (((PdptIndex << 9) + PdIndex) << 21);
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Address = (UINTN) LShiftU64 (
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LShiftU64 (
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LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,
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9
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) + PdIndex,
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21
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);
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//
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// If it is 2M page, check IsAddressSplit()
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@ -619,22 +657,32 @@ InitPaging (
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Pt = AllocatePageTableMemory (1);
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ASSERT (Pt != NULL);
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*Pd = (UINTN) Pt | IA32_PG_RW | IA32_PG_P;
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// Split it
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for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++) {
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Pt[PtIndex] = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
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for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++, Pt++) {
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*Pt = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
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} // end for PT
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*Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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} // end if IsAddressSplit
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} // end for PD
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} // end for PDPT
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} // end for PML4
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} // end for PML5
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//
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// Go through page table and set several page table entries to absent or execute-disable.
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//
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DEBUG ((EFI_D_INFO, "Patch page table start ...\n"));
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for (Pml5Index = 0; Pml5Index < NumberOfPml5Entries; Pml5Index++) {
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if ((Pml5[Pml5Index] & IA32_PG_P) == 0) {
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//
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// If PML5 entry does not exist, skip it
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//
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continue;
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}
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Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
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for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {
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if (sizeof (UINTN) == sizeof (UINT64)) {
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if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {
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//
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// If PML4 entry does not exist, skip it
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@ -642,9 +690,6 @@ InitPaging (
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continue;
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}
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Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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} else {
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Pdpt = (UINT64*)(UINTN)mSmmProfileCr3;
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}
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for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {
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if ((*Pdpt & IA32_PG_P) == 0) {
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//
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@ -672,7 +717,13 @@ InitPaging (
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//
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continue;
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}
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Address = (((PdptIndex << 9) + PdIndex) << 21);
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Address = (UINTN) LShiftU64 (
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LShiftU64 (
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LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,
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9
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) + PdIndex,
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21
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);
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if ((*Pd & IA32_PG_PS) != 0) {
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// 2MB page
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@ -705,6 +756,7 @@ InitPaging (
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} // end for PD
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} // end for PDPT
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} // end for PML4
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} // end for PML5
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//
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// Flush TLB
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@ -1156,6 +1208,20 @@ RestorePageTableBelow4G (
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{
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UINTN PTIndex;
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UINTN PFIndex;
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IA32_CR4 Cr4;
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BOOLEAN Enable5LevelPaging;
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Cr4.UintN = AsmReadCr4 ();
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Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
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//
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// PML5
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//
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if (Enable5LevelPaging) {
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PTIndex = (UINTN)BitFieldRead64 (PFAddress, 48, 56);
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ASSERT (PageTable[PTIndex] != 0);
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PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
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}
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//
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// PML4
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@ -16,6 +16,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool);
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BOOLEAN m1GPageTableSupport = FALSE;
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BOOLEAN mCpuSmmStaticPageTable;
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BOOLEAN m5LevelPagingSupport;
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X86_ASSEMBLY_PATCH_LABEL gPatch5LevelPagingSupport;
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/**
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Disable CET.
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@ -60,6 +62,31 @@ Is1GPageSupport (
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return FALSE;
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}
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/**
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Check if 5-level paging is supported by processor or not.
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@retval TRUE 5-level paging is supported.
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@retval FALSE 5-level paging is not supported.
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**/
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BOOLEAN
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Is5LevelPagingSupport (
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VOID
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)
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{
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CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags;
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AsmCpuidEx (
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CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
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CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
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NULL,
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NULL,
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&EcxFlags.Uint32,
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NULL
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);
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return (BOOLEAN) (EcxFlags.Bits.FiveLevelPage != 0);
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}
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/**
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Set sub-entries number in entry.
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@ -130,14 +157,6 @@ CalculateMaximumSupportAddress (
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PhysicalAddressBits = 36;
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}
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}
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//
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// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
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//
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ASSERT (PhysicalAddressBits <= 52);
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if (PhysicalAddressBits > 48) {
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PhysicalAddressBits = 48;
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}
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return PhysicalAddressBits;
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}
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@ -152,33 +171,80 @@ SetStaticPageTable (
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)
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{
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UINT64 PageAddress;
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UINTN NumberOfPml5EntriesNeeded;
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UINTN NumberOfPml4EntriesNeeded;
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UINTN NumberOfPdpEntriesNeeded;
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UINTN IndexOfPml5Entries;
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UINTN IndexOfPml4Entries;
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UINTN IndexOfPdpEntries;
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UINTN IndexOfPageDirectoryEntries;
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UINT64 *PageMapLevel5Entry;
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UINT64 *PageMapLevel4Entry;
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UINT64 *PageMap;
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UINT64 *PageDirectoryPointerEntry;
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UINT64 *PageDirectory1GEntry;
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UINT64 *PageDirectoryEntry;
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if (mPhysicalAddressBits <= 39 ) {
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NumberOfPml4EntriesNeeded = 1;
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NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (mPhysicalAddressBits - 30));
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} else {
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NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (mPhysicalAddressBits - 39));
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NumberOfPdpEntriesNeeded = 512;
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//
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// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses
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// when 5-Level Paging is disabled.
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//
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ASSERT (mPhysicalAddressBits <= 52);
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if (!m5LevelPagingSupport && mPhysicalAddressBits > 48) {
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mPhysicalAddressBits = 48;
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}
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NumberOfPml5EntriesNeeded = 1;
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if (mPhysicalAddressBits > 48) {
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NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1, mPhysicalAddressBits - 48);
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mPhysicalAddressBits = 48;
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}
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NumberOfPml4EntriesNeeded = 1;
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if (mPhysicalAddressBits > 39) {
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NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1, mPhysicalAddressBits - 39);
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mPhysicalAddressBits = 39;
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}
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NumberOfPdpEntriesNeeded = 1;
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ASSERT (mPhysicalAddressBits > 30);
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NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1, mPhysicalAddressBits - 30);
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//
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// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
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//
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PageMap = (VOID *) PageTable;
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PageMapLevel4Entry = PageMap;
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PageMapLevel5Entry = NULL;
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if (m5LevelPagingSupport) {
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//
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// By architecture only one PageMapLevel5 exists - so lets allocate storage for it.
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//
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PageMapLevel5Entry = PageMap;
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}
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PageAddress = 0;
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for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {
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for ( IndexOfPml5Entries = 0
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; IndexOfPml5Entries < NumberOfPml5EntriesNeeded
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; IndexOfPml5Entries++, PageMapLevel5Entry++) {
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//
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// Each PML5 entry points to a page of PML4 entires.
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// So lets allocate space for them and fill them in in the IndexOfPml4Entries loop.
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// When 5-Level Paging is disabled, below allocation happens only once.
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//
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if (m5LevelPagingSupport) {
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PageMapLevel4Entry = (UINT64 *) ((*PageMapLevel5Entry) & ~mAddressEncMask & gPhyMask);
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if (PageMapLevel4Entry == NULL) {
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PageMapLevel4Entry = AllocatePageTableMemory (1);
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ASSERT(PageMapLevel4Entry != NULL);
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ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE(1));
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*PageMapLevel5Entry = (UINT64)(UINTN)PageMapLevel4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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}
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}
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for (IndexOfPml4Entries = 0; IndexOfPml4Entries < (NumberOfPml5EntriesNeeded == 1 ? NumberOfPml4EntriesNeeded : 512); IndexOfPml4Entries++, PageMapLevel4Entry++) {
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//
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// Each PML4 entry points to a page of Page Directory Pointer entries.
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//
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@ -207,7 +273,7 @@ SetStaticPageTable (
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}
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} else {
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PageAddress = BASE_4GB;
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for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
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for (IndexOfPdpEntries = 0; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded == 1 ? NumberOfPdpEntriesNeeded : 512); IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
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if (IndexOfPml4Entries == 0 && IndexOfPdpEntries < 4) {
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//
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// Skip the < 4G entries
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@ -239,6 +305,7 @@ SetStaticPageTable (
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}
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}
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}
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}
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}
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/**
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@ -259,6 +326,8 @@ SmmInitPageTable (
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UINTN PageFaultHandlerHookAddress;
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IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
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EFI_STATUS Status;
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UINT64 *Pml4Entry;
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UINT64 *Pml5Entry;
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//
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// Initialize spin lock
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@ -267,11 +336,13 @@ SmmInitPageTable (
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mCpuSmmStaticPageTable = PcdGetBool (PcdCpuSmmStaticPageTable);
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m1GPageTableSupport = Is1GPageSupport ();
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DEBUG ((DEBUG_INFO, "1GPageTableSupport - 0x%x\n", m1GPageTableSupport));
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DEBUG ((DEBUG_INFO, "PcdCpuSmmStaticPageTable - 0x%x\n", mCpuSmmStaticPageTable));
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m5LevelPagingSupport = Is5LevelPagingSupport ();
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mPhysicalAddressBits = CalculateMaximumSupportAddress ();
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DEBUG ((DEBUG_INFO, "PhysicalAddressBits - 0x%x\n", mPhysicalAddressBits));
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PatchInstructionX86 (gPatch5LevelPagingSupport, m5LevelPagingSupport, 1);
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DEBUG ((DEBUG_INFO, "5LevelPaging Support - %d\n", m5LevelPagingSupport));
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DEBUG ((DEBUG_INFO, "1GPageTable Support - %d\n", m1GPageTableSupport));
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DEBUG ((DEBUG_INFO, "PcdCpuSmmStaticPageTable - %d\n", mCpuSmmStaticPageTable));
|
||||
DEBUG ((DEBUG_INFO, "PhysicalAddressBits - %d\n", mPhysicalAddressBits));
|
||||
//
|
||||
// Generate PAE page table for the first 4GB memory space
|
||||
//
|
||||
|
|
@ -288,15 +359,30 @@ SmmInitPageTable (
|
|||
//
|
||||
// Fill Page-Table-Level4 (PML4) entry
|
||||
//
|
||||
PTEntry = (UINT64*)AllocatePageTableMemory (1);
|
||||
ASSERT (PTEntry != NULL);
|
||||
*PTEntry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
|
||||
ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));
|
||||
Pml4Entry = (UINT64*)AllocatePageTableMemory (1);
|
||||
ASSERT (Pml4Entry != NULL);
|
||||
*Pml4Entry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
|
||||
ZeroMem (Pml4Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml4Entry));
|
||||
|
||||
//
|
||||
// Set sub-entries number
|
||||
//
|
||||
SetSubEntriesNum (PTEntry, 3);
|
||||
SetSubEntriesNum (Pml4Entry, 3);
|
||||
PTEntry = Pml4Entry;
|
||||
|
||||
if (m5LevelPagingSupport) {
|
||||
//
|
||||
// Fill PML5 entry
|
||||
//
|
||||
Pml5Entry = (UINT64*)AllocatePageTableMemory (1);
|
||||
*Pml5Entry = (UINTN) Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
|
||||
ZeroMem (Pml5Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml5Entry));
|
||||
//
|
||||
// Set sub-entries number
|
||||
//
|
||||
SetSubEntriesNum (Pml5Entry, 1);
|
||||
PTEntry = Pml5Entry;
|
||||
}
|
||||
|
||||
if (mCpuSmmStaticPageTable) {
|
||||
SetStaticPageTable ((UINTN)PTEntry);
|
||||
|
|
@ -344,7 +430,7 @@ SmmInitPageTable (
|
|||
}
|
||||
|
||||
//
|
||||
// Return the address of PML4 (to set CR3)
|
||||
// Return the address of PML4/PML5 (to set CR3)
|
||||
//
|
||||
return (UINT32)(UINTN)PTEntry;
|
||||
}
|
||||
|
|
@ -436,12 +522,16 @@ ReclaimPages (
|
|||
VOID
|
||||
)
|
||||
{
|
||||
UINT64 Pml5Entry;
|
||||
UINT64 *Pml5;
|
||||
UINT64 *Pml4;
|
||||
UINT64 *Pdpt;
|
||||
UINT64 *Pdt;
|
||||
UINTN Pml5Index;
|
||||
UINTN Pml4Index;
|
||||
UINTN PdptIndex;
|
||||
UINTN PdtIndex;
|
||||
UINTN MinPml5;
|
||||
UINTN MinPml4;
|
||||
UINTN MinPdpt;
|
||||
UINTN MinPdt;
|
||||
|
|
@ -451,21 +541,44 @@ ReclaimPages (
|
|||
BOOLEAN PML4EIgnore;
|
||||
BOOLEAN PDPTEIgnore;
|
||||
UINT64 *ReleasePageAddress;
|
||||
IA32_CR4 Cr4;
|
||||
BOOLEAN Enable5LevelPaging;
|
||||
|
||||
Pml4 = NULL;
|
||||
Pdpt = NULL;
|
||||
Pdt = NULL;
|
||||
MinAcc = (UINT64)-1;
|
||||
MinPml4 = (UINTN)-1;
|
||||
MinPml5 = (UINTN)-1;
|
||||
MinPdpt = (UINTN)-1;
|
||||
MinPdt = (UINTN)-1;
|
||||
Acc = 0;
|
||||
ReleasePageAddress = 0;
|
||||
|
||||
Cr4.UintN = AsmReadCr4 ();
|
||||
Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
|
||||
Pml5 = (UINT64*)(UINTN)(AsmReadCr3 () & gPhyMask);
|
||||
|
||||
if (!Enable5LevelPaging) {
|
||||
//
|
||||
// Create one fake PML5 entry for 4-Level Paging
|
||||
// so that the page table parsing logic only handles 5-Level page structure.
|
||||
//
|
||||
Pml5Entry = (UINTN) Pml5 | IA32_PG_P;
|
||||
Pml5 = &Pml5Entry;
|
||||
}
|
||||
|
||||
//
|
||||
// First, find the leaf entry has the smallest access record value
|
||||
//
|
||||
Pml4 = (UINT64*)(UINTN)(AsmReadCr3 () & gPhyMask);
|
||||
for (Pml5Index = 0; Pml5Index < Enable5LevelPaging ? (EFI_PAGE_SIZE / sizeof (*Pml4)) : 1; Pml5Index++) {
|
||||
if ((Pml5[Pml5Index] & IA32_PG_P) == 0 || (Pml5[Pml5Index] & IA32_PG_PMNT) != 0) {
|
||||
//
|
||||
// If the PML5 entry is not present or is masked, skip it
|
||||
//
|
||||
continue;
|
||||
}
|
||||
Pml4 = (UINT64*)(UINTN)(Pml5[Pml5Index] & gPhyMask);
|
||||
for (Pml4Index = 0; Pml4Index < EFI_PAGE_SIZE / sizeof (*Pml4); Pml4Index++) {
|
||||
if ((Pml4[Pml4Index] & IA32_PG_P) == 0 || (Pml4[Pml4Index] & IA32_PG_PMNT) != 0) {
|
||||
//
|
||||
|
|
@ -522,6 +635,7 @@ ReclaimPages (
|
|||
// save the Page address to be released
|
||||
//
|
||||
MinAcc = Acc;
|
||||
MinPml5 = Pml5Index;
|
||||
MinPml4 = Pml4Index;
|
||||
MinPdpt = PdptIndex;
|
||||
MinPdt = PdtIndex;
|
||||
|
|
@ -541,6 +655,7 @@ ReclaimPages (
|
|||
// save the Page address to be released
|
||||
//
|
||||
MinAcc = Acc;
|
||||
MinPml5 = Pml5Index;
|
||||
MinPml4 = Pml4Index;
|
||||
MinPdpt = PdptIndex;
|
||||
MinPdt = (UINTN)-1;
|
||||
|
|
@ -561,6 +676,7 @@ ReclaimPages (
|
|||
// save the Page address to be released
|
||||
//
|
||||
MinAcc = Acc;
|
||||
MinPml5 = Pml5Index;
|
||||
MinPml4 = Pml4Index;
|
||||
MinPdpt = (UINTN)-1;
|
||||
MinPdt = (UINTN)-1;
|
||||
|
|
@ -568,6 +684,7 @@ ReclaimPages (
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
//
|
||||
// Make sure one PML4/PDPT/PD entry is selected
|
||||
//
|
||||
|
|
@ -588,6 +705,7 @@ ReclaimPages (
|
|||
//
|
||||
// If 4 KByte Page Table is released, check the PDPT entry
|
||||
//
|
||||
Pml4 = (UINT64 *) (UINTN) (Pml5[MinPml5] & gPhyMask);
|
||||
Pdpt = (UINT64*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask);
|
||||
SubEntriesNum = GetSubEntriesNum(Pdpt + MinPdpt);
|
||||
if (SubEntriesNum == 0) {
|
||||
|
|
@ -679,7 +797,7 @@ SmiDefaultPFHandler (
|
|||
)
|
||||
{
|
||||
UINT64 *PageTable;
|
||||
UINT64 *Pml4;
|
||||
UINT64 *PageTableTop;
|
||||
UINT64 PFAddress;
|
||||
UINTN StartBit;
|
||||
UINTN EndBit;
|
||||
|
|
@ -690,6 +808,8 @@ SmiDefaultPFHandler (
|
|||
UINTN PageAttribute;
|
||||
EFI_STATUS Status;
|
||||
UINT64 *UpperEntry;
|
||||
BOOLEAN Enable5LevelPaging;
|
||||
IA32_CR4 Cr4;
|
||||
|
||||
//
|
||||
// Set default SMM page attribute
|
||||
|
|
@ -699,9 +819,12 @@ SmiDefaultPFHandler (
|
|||
PageAttribute = 0;
|
||||
|
||||
EndBit = 0;
|
||||
Pml4 = (UINT64*)(AsmReadCr3 () & gPhyMask);
|
||||
PageTableTop = (UINT64*)(AsmReadCr3 () & gPhyMask);
|
||||
PFAddress = AsmReadCr2 ();
|
||||
|
||||
Cr4.UintN = AsmReadCr4 ();
|
||||
Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 != 0);
|
||||
|
||||
Status = GetPlatformPageTableAttribute (PFAddress, &PageSize, &NumOfPages, &PageAttribute);
|
||||
//
|
||||
// If platform not support page table attribute, set default SMM page attribute
|
||||
|
|
@ -755,9 +878,9 @@ SmiDefaultPFHandler (
|
|||
}
|
||||
|
||||
for (Index = 0; Index < NumOfPages; Index++) {
|
||||
PageTable = Pml4;
|
||||
PageTable = PageTableTop;
|
||||
UpperEntry = NULL;
|
||||
for (StartBit = 39; StartBit > EndBit; StartBit -= 9) {
|
||||
for (StartBit = Enable5LevelPaging ? 48 : 39; StartBit > EndBit; StartBit -= 9) {
|
||||
PTIndex = BitFieldRead64 (PFAddress, StartBit, StartBit + 8);
|
||||
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
|
||||
//
|
||||
|
|
@ -941,13 +1064,20 @@ SetPageTableAttributes (
|
|||
UINTN Index2;
|
||||
UINTN Index3;
|
||||
UINTN Index4;
|
||||
UINTN Index5;
|
||||
UINT64 *L1PageTable;
|
||||
UINT64 *L2PageTable;
|
||||
UINT64 *L3PageTable;
|
||||
UINT64 *L4PageTable;
|
||||
UINT64 *L5PageTable;
|
||||
BOOLEAN IsSplitted;
|
||||
BOOLEAN PageTableSplitted;
|
||||
BOOLEAN CetEnabled;
|
||||
IA32_CR4 Cr4;
|
||||
BOOLEAN Enable5LevelPaging;
|
||||
|
||||
Cr4.UintN = AsmReadCr4 ();
|
||||
Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
|
||||
|
||||
//
|
||||
// Don't do this if
|
||||
|
|
@ -991,8 +1121,22 @@ SetPageTableAttributes (
|
|||
do {
|
||||
DEBUG ((DEBUG_INFO, "Start...\n"));
|
||||
PageTableSplitted = FALSE;
|
||||
L5PageTable = NULL;
|
||||
if (Enable5LevelPaging) {
|
||||
L5PageTable = (UINT64 *)GetPageTableBase ();
|
||||
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L5PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
|
||||
PageTableSplitted = (PageTableSplitted || IsSplitted);
|
||||
}
|
||||
|
||||
for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof(UINT64) : 1); Index5++) {
|
||||
if (Enable5LevelPaging) {
|
||||
L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
|
||||
if (L4PageTable == NULL) {
|
||||
continue;
|
||||
}
|
||||
} else {
|
||||
L4PageTable = (UINT64 *)GetPageTableBase ();
|
||||
}
|
||||
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
|
||||
PageTableSplitted = (PageTableSplitted || IsSplitted);
|
||||
|
||||
|
|
@ -1032,6 +1176,7 @@ SetPageTableAttributes (
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
} while (PageTableSplitted);
|
||||
|
||||
//
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@ extern ASM_PFX(mXdSupported)
|
|||
global ASM_PFX(gPatchXdSupported)
|
||||
global ASM_PFX(gPatchSmiStack)
|
||||
global ASM_PFX(gPatchSmiCr3)
|
||||
global ASM_PFX(gPatch5LevelPagingSupport)
|
||||
global ASM_PFX(gcSmiHandlerTemplate)
|
||||
global ASM_PFX(gcSmiHandlerSize)
|
||||
|
||||
|
|
@ -124,6 +125,17 @@ ProtFlatMode:
|
|||
ASM_PFX(gPatchSmiCr3):
|
||||
mov cr3, rax
|
||||
mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3
|
||||
|
||||
mov cl, strict byte 0 ; source operand will be patched
|
||||
ASM_PFX(gPatch5LevelPagingSupport):
|
||||
cmp cl, 0
|
||||
je SkipEnable5LevelPaging
|
||||
;
|
||||
; Enable 5-Level Paging bit
|
||||
;
|
||||
bts eax, 12 ; Set LA57 bit (bit #12)
|
||||
SkipEnable5LevelPaging:
|
||||
|
||||
mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
|
||||
; Load TSS
|
||||
sub esp, 8 ; reserve room in stack
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
X64 processor specific functions to enable SMM profile.
|
||||
|
||||
Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
|
@ -147,9 +147,14 @@ RestorePageTableAbove4G (
|
|||
BOOLEAN Existed;
|
||||
UINTN Index;
|
||||
UINTN PFIndex;
|
||||
IA32_CR4 Cr4;
|
||||
BOOLEAN Enable5LevelPaging;
|
||||
|
||||
ASSERT ((PageTable != NULL) && (IsValidPFAddress != NULL));
|
||||
|
||||
Cr4.UintN = AsmReadCr4 ();
|
||||
Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
|
||||
|
||||
//
|
||||
// If page fault address is 4GB above.
|
||||
//
|
||||
|
|
@ -161,6 +166,15 @@ RestorePageTableAbove4G (
|
|||
//
|
||||
Existed = FALSE;
|
||||
PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
|
||||
PTIndex = 0;
|
||||
if (Enable5LevelPaging) {
|
||||
PTIndex = BitFieldRead64 (PFAddress, 48, 56);
|
||||
}
|
||||
if ((!Enable5LevelPaging) || ((PageTable[PTIndex] & IA32_PG_P) != 0)) {
|
||||
// PML5E
|
||||
if (Enable5LevelPaging) {
|
||||
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
|
||||
}
|
||||
PTIndex = BitFieldRead64 (PFAddress, 39, 47);
|
||||
if ((PageTable[PTIndex] & IA32_PG_P) != 0) {
|
||||
// PML4E
|
||||
|
|
@ -197,6 +211,7 @@ RestorePageTableAbove4G (
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// If page entry does not existed in page table at all, create a new entry.
|
||||
|
|
@ -221,6 +236,11 @@ RestorePageTableAbove4G (
|
|||
//
|
||||
PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
|
||||
PFAddress = AsmReadCr2 ();
|
||||
// PML5E
|
||||
if (Enable5LevelPaging) {
|
||||
PTIndex = BitFieldRead64 (PFAddress, 48, 56);
|
||||
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
|
||||
}
|
||||
// PML4E
|
||||
PTIndex = BitFieldRead64 (PFAddress, 39, 47);
|
||||
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
|
||||
|
|
|
|||
Loading…
Reference in New Issue