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ArmPkg/ArmGic: Move GICv2 specific EOI/ACK routines into v2 driver

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ArmGicDxe is the only remaining user of ArmGicLib, and so there is no
need for the abstraction, which is drawn at an arbitrary boundary
anyway. So remove the remaining V2 specific code into the DXE driver.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Ard Biesheuvel 2025-01-16 17:02:36 +01:00 committed by mergify[bot]
parent 337a99af10
commit 84eed1ef2a
4 changed files with 50 additions and 68 deletions
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4
ArmPkg/Drivers/ArmGic/ArmGicLib.inf
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@ -13,10 +13,6 @@
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmGicLib
[Sources]
GicV2/ArmGicV2Lib.c
GicV2/ArmGicV2NonSecLib.c
[Sources.ARM]
GicV3/Arm/ArmGicV3.S | GCC

50
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
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@ -22,6 +22,11 @@ Abstract:
#define ARM_GIC_DEFAULT_PRIORITY 0x80
// Interrupts from 1020 to 1023 are considered as special interrupts
// (eg: spurious interrupts)
#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \
(((Interrupt) >= 1020) && ((Interrupt) <= 1023))
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
@ -181,6 +186,27 @@ GicV2GetInterruptSourceState (
return EFI_SUCCESS;
}
STATIC
UINTN
ArmGicV2AcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase
)
{
// Read the Interrupt Acknowledge Register
return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
}
STATIC
VOID
ArmGicV2EndOfInterrupt (
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
)
{
ASSERT (Source <= MAX_UINT32);
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, (UINT32)Source);
}
/**
Signal to the hardware that the End Of Interrupt state
has been reached.
@ -408,6 +434,30 @@ EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
GicV2SetTriggerType
};
STATIC
VOID
ArmGicV2EnableInterruptInterface (
IN UINTN GicInterruptInterfaceBase
)
{
/*
* Enable the CPU interface in Non-Secure world
* Note: The ICCICR register is banked when Security extensions are implemented
*/
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
}
STATIC
VOID
ArmGicV2DisableInterruptInterface (
IN UINTN GicInterruptInterfaceBase
)
{
// Disable Gic Interface
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);
}
/**
Shutdown our hardware

32
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c
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@ -1,32 +0,0 @@
/** @file
*
* Copyright (c) 2013-2023, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/ArmGicLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
UINTN
EFIAPI
ArmGicV2AcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase
)
{
// Read the Interrupt Acknowledge Register
return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
}
VOID
EFIAPI
ArmGicV2EndOfInterrupt (
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
)
{
ASSERT (Source <= MAX_UINT32);
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, (UINT32)Source);
}

32
ArmPkg/Include/Library/ArmGicLib.h
View File

@ -110,38 +110,6 @@
// Bit Mask for
#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
// GIC revision 2 specific declarations
// Interrupts from 1020 to 1023 are considered as special interrupts
// (eg: spurious interrupts)
#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \
(((Interrupt) >= 1020) && ((Interrupt) <= 1023))
VOID
EFIAPI
ArmGicV2EnableInterruptInterface (
IN UINTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2DisableInterruptInterface (
IN UINTN GicInterruptInterfaceBase
);
UINTN
EFIAPI
ArmGicV2AcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2EndOfInterrupt (
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
);
// GIC revision 3 specific declarations
#define ICC_SRE_EL2_SRE (1 << 0)