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ArmPkg: Add isb when setting SCR 

Some updates to SCR can cause a problem which manifests as an undefined opcode exception.
This may be when a speculative secure instruction fetch happens after the NS bit is set.
An isb is required to make the register change take effect fully.

Contributed-under: Tianocore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <Evan.Lloyd@arm.com>
Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Evan Lloyd 2016-02-03 17:07:47 +00:00 committed by Leif Lindholm
parent 0119b06607
commit b2d0e0c51a
3 changed files with 3 additions and 0 deletions
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1
ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
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@ -184,6 +184,7 @@ ASM_PFX(ArmWriteCptr):
ASM_PFX(ArmWriteScr): ASM_PFX(ArmWriteScr):
msr scr_el3, x0 // Secure configuration register EL3 msr scr_el3, x0 // Secure configuration register EL3
isb
ret ret
ASM_PFX(ArmWriteMVBar): ASM_PFX(ArmWriteMVBar):

1
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
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@ -147,6 +147,7 @@ ASM_PFX(ArmReadScr):
ASM_PFX(ArmWriteScr): ASM_PFX(ArmWriteScr):
mcr p15, 0, r0, c1, c1, 0 mcr p15, 0, r0, c1, c1, 0
isb
bx lr bx lr
ASM_PFX(ArmReadHVBar): ASM_PFX(ArmReadHVBar):

1
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
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@ -121,6 +121,7 @@
RVCT_ASM_EXPORT ArmWriteScr RVCT_ASM_EXPORT ArmWriteScr
mcr p15, 0, r0, c1, c1, 0 mcr p15, 0, r0, c1, c1, 0
isb
bx lr bx lr
RVCT_ASM_EXPORT ArmReadHVBar RVCT_ASM_EXPORT ArmReadHVBar