ArmPkg: Add isb when setting SCR

Some updates to SCR can cause a problem which manifests as an undefined opcode exception.
This may be when a speculative secure instruction fetch happens after the NS bit is set.
An isb is required to make the register change take effect fully.

Contributed-under: Tianocore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <Evan.Lloyd@arm.com>
Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S

@@ -184,6 +184,7 @@ ASM_PFX(ArmWriteCptr):
 
 ASM_PFX(ArmWriteScr):
   msr     scr_el3, x0            // Secure configuration register EL3
+  isb
   ret
 
 ASM_PFX(ArmWriteMVBar):

ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S

@@ -147,6 +147,7 @@ ASM_PFX(ArmReadScr):
 
 ASM_PFX(ArmWriteScr):
   mcr     p15, 0, r0, c1, c1, 0
+  isb
   bx      lr
 
 ASM_PFX(ArmReadHVBar):

ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm

@@ -121,6 +121,7 @@
 
  RVCT_ASM_EXPORT ArmWriteScr
   mcr     p15, 0, r0, c1, c1, 0
+  isb
   bx      lr
 
  RVCT_ASM_EXPORT ArmReadHVBar