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UefiCpuPkg: RiscV64: initialize FPU
The OpenSSL library uses floating point registers. The is no guarantee that a prior firmware stage has enabled the FPU. Provide a library BaseRiscVFpuLib to * Enable the FPU and set it to state 'dirty'. * Clear the fcsr CSR. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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@ -359,6 +359,12 @@ InitializeCpu (
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Status = RiscVConfigureMmu ();
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Status = RiscVConfigureMmu ();
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ASSERT_EFI_ERROR (Status);
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ASSERT_EFI_ERROR (Status);
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//
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// Initialize FPU
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//
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Status = RiscVInitializeFpu ();
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ASSERT_EFI_ERROR (Status);
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//
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//
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// Install Boot protocol
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// Install Boot protocol
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//
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//
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@ -14,6 +14,7 @@
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#include <Protocol/Cpu.h>
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#include <Protocol/Cpu.h>
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#include <Protocol/RiscVBootProtocol.h>
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#include <Protocol/RiscVBootProtocol.h>
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#include <Library/BaseRiscVFpuLib.h>
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#include <Library/BaseRiscVSbiLib.h>
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#include <Library/BaseRiscVSbiLib.h>
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#include <Library/BaseRiscVMmuLib.h>
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#include <Library/BaseRiscVMmuLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseLib.h>
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@ -38,6 +38,7 @@
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PeCoffGetEntryPointLib
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PeCoffGetEntryPointLib
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RiscVSbiLib
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RiscVSbiLib
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RiscVMmuLib
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RiscVMmuLib
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RiscVFpuLib
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CacheMaintenanceLib
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CacheMaintenanceLib
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[Sources]
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[Sources]
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21
UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h
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21
UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h
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@ -0,0 +1,21 @@
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/** @file
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Copyright (c) 2024, Canonical Services Ltd<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef BASE_RISCV_FPU_LIB_H_
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#define BASE_RISCV_FPU_LIB_H_
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/**
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Initialize floating point unit
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**/
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EFI_STATUS
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EFIAPI
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RiscVInitializeFpu (
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VOID
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);
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#endif /* BASE_RISCV_FPU_LIB_H_ */
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26
UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf
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UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf
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@ -0,0 +1,26 @@
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## @file
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# RISC-V FPU library.
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#
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# Copyright (c) 2024, Canonical Services Ltd
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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INF_VERSION = 0x0001001b
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BASE_NAME = BaseRiscVFpuLib
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FILE_GUID = e600fe4d-8595-40f3-90a0-5f043ce155c2
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = RiscVFpuLib
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[Sources]
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RiscVFpuCore.S
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[Packages]
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MdePkg/MdePkg.dec
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UefiCpuPkg/UefiCpuPkg.dec
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[LibraryClasses]
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BaseLib
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22
UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S
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UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S
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@ -0,0 +1,22 @@
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/** @file
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*
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* Copyright (c) 2024, Canonical Services Ltd
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Library/BaseRiscVFpuLib.h>
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#include <Register/RiscV64/RiscVImpl.h>
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//
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// Initialize floating point unit
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//
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ASM_FUNC (RiscVInitializeFpu)
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csrr a0, CSR_SSTATUS
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li a1, MSTATUS_FS
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or a0, a0, a1
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csrw CSR_SSTATUS, a0
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csrw CSR_FCSR, x0
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li a0, 0
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ret
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@ -75,6 +75,8 @@
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SmmRelocationLib|Include/Library/SmmRelocationLib.h
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SmmRelocationLib|Include/Library/SmmRelocationLib.h
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[LibraryClasses.RISCV64]
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[LibraryClasses.RISCV64]
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## @libraryclass Provides function to initialize the FPU.
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RiscVFpuLib|Include/Library/BaseRiscVFpuLib.h
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## @libraryclass Provides functions to manage MMU features on RISCV64 CPUs.
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## @libraryclass Provides functions to manage MMU features on RISCV64 CPUs.
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##
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##
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RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h
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RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h
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@ -224,6 +224,7 @@
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[Components.RISCV64]
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[Components.RISCV64]
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UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
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UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
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UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
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UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
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UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf
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UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
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UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
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UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
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UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
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UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
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UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
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