BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3223
In the current design, memory protection is not available till CpuDxe
is loaded. To resolve this, introduce CpuArchLib to move the
CPU Architectural initialization to DxeCore.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Vitaly Cheptsov <vit9696@protonmail.com>
Signed-off-by: Marvin Häuser <mhaeuser@posteo.de>
Added missing EFIAPI modifier to SmmSwDispatcher function which passed into gSmst->SmiHandlerRegister routine.
Signed-off-by: Savva Mitrofanov <sk.mitrofanov@ispras.ru>
Reviewed-by: Vitaly Cheptsov <cheptsov@ispras.ru>
Commit efbf5ed moves StackCheckLibStaticInit to StackCheckLib,
and each SEC module has a dependency on StackCheckLib now.
Add StackCheckLib in FitUniversalPayloadEntry.inf to fix build
issue.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
This commit oves StackCheckLib from a NULL lib to an instance of
StackCheckLib. This requires every entry point to add a library
dependency on StackCheckLib. It also requires every SEC module
to have a dependency on StackCheckLib because there is no
standard SEC entry point.
It allows for greater flexibility for a platform to apply stack
cookies and simplifies DSC logic.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
With the latest GccBase.lds combining with CLANG build, there is no
need to enforce 4KB alignment of in UPL CLANGDWARF build.
This reverts commit b3bfb8f22d43bd9577df85bec20e75eb2f659990.
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Original ELF segment/section syncup process having layout assumption
which has caused build failure when layout changing.
New process will parse both existing segments and sections firstly to
support different layout.
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
After commit aca75d3 the PayloadEntry ELF header will miss dynamic
section which caused PEI_ASSERT in PayloadLoader rebasing code.
This commit adding common-page-size=0x1000 to CLANGDWARF_DLINK_FLAGS
to overcome the ELF header generation issue.
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Merge the PCI root bridge with the same segment address within one.
PciSegment element.
UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
Signed-off-by: Linus Liu <linus.liu@intel.com>
In platform which support ACPI 2.0 only, the base address of ACPI region
is not page aligned. This unalinged base address leads to failure at
BuildMemoryAllocationHob when parsing ACPI node in FdtParserLib, before
building gUniversalPayloadAcpiTableGuid GUID HOB.
Align base address of ACPI region down to EFI_PAGE_SIZE to make sure
base address always aligned.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
PixelsPerScanLine is required in some UEFI capable OS distribution.
To align with simple-framebuffer definition in kernel Documentation:
devicetree/bindings/display/simple-framebuffer.txt, no property node
will be introduced for PixelsPerScanLine.
Set value of PixelsPerScanLine to HorizontalResolution, as they are
identical in most cases.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
Current implementation only supports serial port sub-node under
PCI root bridge node.
This enhancement support serial port node regardless it is under
root node or PCI root bridge node using a single FDT passing function.
Signed-off-by: Guo Dong <guo.dong@intel.com>
According to ACPI Specification, 64 bit physical address of the XSDT
provides indentical functionality to the RSDT but accommodates physical
address of description headers that are larger than 32 bits.
In this case physical address of XSDT table is 64 bit aligned, however
size of ACPI description tabled header is not 64 bit aligned. It leads
to the entry of other description headers are not 64 bit aligned. In
AARCH64 architecture, deference non-aligned 64 bit address to fetch
64-bit data will trigger Alignment fault. Use ReadUnaligned64 method
to fix this unaligned data access issue.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
If alignment check is enabled in AARCH64 platform, FDT parser might
dereference non-aligned 64-bit address to fetch 64-bit data.
Use unaligned data read to avoid triggering unaligned data access.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4873
Currently the function does not cover the 5 level paging case. it will
casued pagetable protection region set incorrectly. This patch do the
enhancemant and with the patch protection region has been set correctly.
Signed-off-by: Ning Feng <ning.feng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Now that the ResetVectors are USER_DEFINED modules, they will not
be linked against StackCheckLibNull, which were the only modules
causing issues. So, we can now remove the kludge we had before
and the requirement for every DSC to include StackCheckLibNull
for SEC modules and just apply StackCheckLibNull globally.
This also changes every DSC to drop the SEC definition of
StackCheckLibNull.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
There are couples of gUniversalPayloadAcpiTableGuid in
payload , only build one
gUniversalPayloadAcpiTableGuid hob and acpi memory hob.
when the reserved memory address matched the rsdp.
Signed-off-by: Linus Liu <linus.liu@intel.com>
Per other platform request , need to add SMBIOS device node into FDT.
In the current phase(1) , only supporting SM3EntryPoint structure.
Signed-off-by: Linus Liu <linus.liu@intel.com>
Introduce Secure Boot functionality within UefiPayloadPkg by adding
necessary modules and configurations. A new build flag,
`SECURE_BOOT_ENABLE`, is introduced to control the activation of
Secure Boot.
This patch also overrides values in SecurityPkg to enforce image
verification from all sources.
A new FV (`SECURITY_FV`) for security modules is added for components
and the firmware volume sizes to accommodate additional Secure Boot
components.
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: James Lu <james.lu@intel.com>
Cc: Gua Guo <gua.guo@intel.com>
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Adjust the sequence of gEfiEndOfPeiSignalPpiGuid notify function
when FDT is disabled , or some of notify functions won't work
cause the debug message print twice.
Signed-off-by: Linus Liu <linus.liu@intel.com>
There is currently a mix on functions named as Prop or Property.
The latter is in majority, and the better fit for tianocore coding style,
so rename FdtNodeOffsetByPropValue () and FdtSetProp () for consistency.
To avoid breaking bisect, change existing users in UefiPayloadPkg.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
FdtNumRsv and FdtGetMemRsv were added for the benefit of UefiPayloadPkg,
but their naming matches neither upstream libfdt nor tianocore coding
style rules. And there was scope for improvement of the doxygen
descriptions as well.
These functions currently have only one in-tree user, UefiPayloadPkg
FdtParserLib. So rename them more conformant
FdtGetNumberOfReserveMapEntries
and
FdtGetReserveMapEntry
and update the description comment blocks, at the same time as
updating the existing user.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
S3 performance table is saved to LockBox. Without LockBox, S3 performance
data will lost.
Add LOCKBOX_SUPPORT to optionally select LockBox libary instance,
default value is FALSE.
Signed-off-by: Zhou Jianfeng <jianfeng.zhou@intel.com>
Currently, FIT Payload data relocation data has
some minor error with Universal Payload
Specification v0.9.1 section 2.4.3.
Signed-off-by: Gua Guo <gua.guo@intel.com>
ACPI FADT HW register interface fields are
optional but current UPL common entry code made it
as mandatory which caused compatibility issue on
some platforms.
Solution is to move those FADT HW register fields
check code to consumer code so only ASSERT when
those fields are consumed with error.
Currently only AcpiTimerLib and ResetSystemLib
consuming those register fields so if platforms
configured UPL to different library instances the
FADT HW register fields are not consumed thus will
not cause ASSERT.
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
DT has a way to provide reserved images in a simpler tabular
manner. UPL should be able to support that.
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
In order to properly enable multisegment RB, we need
to grab ecam data from the FDT for each bridge.
Current UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES struct from
MdeModulePkg does not include definition for ecam. In
order to maintain backward compatibility and also avoid
diverging too much from core, we are going to define a
new HOB for UPL segment information and pass it to
GetPciSegmentInfo function. Ths function then grabs specifically
ecam info from the segment hob along with other rb specific
information to create final RB info required by multi segment
PCI driver.
Additionally we would like to support legacy implementations which
rely on ACPIBoard HOB to fill up segment info. So if UplSegmentInfo Hob
is not found we try and look for other hob.
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
We need to let UEFI know that there are cetain memory types
which are special purpose (CXL/HBM) etc and we may want to
avoid using them for UEFI purposes. Hence UPL needs to know
about such memory types.
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
We do not need to go deep into verifying all ACPI tables
at this stage. TODO: Just a simple ACPI header signature
check should be good enough. For now just commenting out
asserts that mandate one to have various tables which is
not applicable to all platforms.
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
As per specification we are going to accept only one argument
at the entry point which is FDT pointer. Grab that and call
the entry point.
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
